A message-based fault diagnosis procedure
SIGCOMM '86 Proceedings of the ACM SIGCOMM conference on Communications architectures & protocols
Fault-tolerant decoders for cyclic error-correcting codes
IEEE Transactions on Computers
The Cubical Ring Connected Cycles: A Fault Tolerant Parallel Computation Network
IEEE Transactions on Computers
ACM SIGARCH Computer Architecture News
DFTEXPERT: an expert system for design of testable VLSI circuits
IEA/AIE '88 Proceedings of the 1st international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1
A Functional Testing Method for Microprocessors
IEEE Transactions on Computers
From defects to failures: a view of dependable computing
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
A General Constructive Approach to Fault-Tolerant Design Using Redundancy
IEEE Transactions on Computers
Design methodology and microdiagnostics development for a self-checking microprocessor
MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
On Distributed Fault Simulation
Computer
IEEE Transactions on Computers
High-level synthesis of fault-secure microarchitectures
DAC '93 Proceedings of the 30th international Design Automation Conference
A Versatile Ring-Connected Hypercube
IEEE Micro
Fault tolerant and BIST design of a FIFO cell
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A Self-Testing Nonincreasing Order Checker
IEEE Transactions on Computers
A New Design Method for Self-Checking Unidirectional Combinational Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
EXFI: a low-cost fault injection system for embedded microprocessor-based boards
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Teraflops Supercomputer: Architecture and Validation of the Fault Tolerance Mechanisms
IEEE Transactions on Computers
Intermediacy Prediction for High Speed Berger Code Checkers
Journal of Electronic Testing: Theory and Applications
Test patterns for fault-tolerant logic circuits using block design concepts
ACM-SE 30 Proceedings of the 30th annual Southeast regional conference
Embryonics: A Bio-Inspired Cellular Architecture with Fault-Tolerant Properties
Genetic Programming and Evolvable Machines
Fault Diagnosis in Analog Circuits Using Element Modulation
IEEE Design & Test
Concurrent Error Detection Using Monitoring Machines
IEEE Design & Test
Implementing Degradable Processing Arrays
IEEE Micro
Fault Tolerance in Multiprocessor Systems Without Dedicated Redundancy
IEEE Transactions on Computers
Generalized Hopfield Neural Network for Concurrent Testing
IEEE Transactions on Computers
Automatic Synthesis of Self-Recovering VLSI Systems
IEEE Transactions on Computers
Reconfiguration and Analysis of a Fault-Tolerant Circular Butterfly Parallel System
IEEE Transactions on Parallel and Distributed Systems
A Pairwise Substitutional Fault Tolerance Technique for the Cube-Connected Cycles Architecture
IEEE Transactions on Parallel and Distributed Systems
Xception: A Technique for the Experimental Evaluation of Dependability in Modern Computers
IEEE Transactions on Software Engineering
A survey of communication protocol testing
Journal of Systems and Software
Assessing Error Detection Coverage by Simulated Fault Injection
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Empirical Assessment of Software On-Line Diagnostics Using Fault Injection
SAFECOMP '00 Proceedings of the 19th International Conference on Computer Safety, Reliability and Security
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
A fault injection environment for microprocessor-based boards
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Error Detection in Polynomial Basis Multipliers over Binary Extension Fields
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers
Journal of Electronic Testing: Theory and Applications
Fault-tolerant systems with concurrent error-locating capability
Journal of Computer Science and Technology
Generalized modular design of testable m-out-of-n code checker
ATS '95 Proceedings of the 4th Asian Test Symposium
Self-checking architectures for fast Hartley transform
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Testing scheme for IC's clocks
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Experimental assessment of parallel systems
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
A new methodology for the design of low-cost fail safe circuits and networks
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A Parameterized VHDL Library for On-Line Testing
ITC '97 Proceedings of the 1997 IEEE International Test Conference
How Seriously Do You Take Possible-Detect Faults?
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Feasibility and Effectiveness of the Algorithm for Overhead Reduction in Analog Checkers
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
A conceptual model for increasing utilization of dependable computer networks
Data & Knowledge Engineering
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Towards fault-tolerant cryptographic computations over finite fields
ACM Transactions on Embedded Computing Systems (TECS)
Reliability assessment in embryonics inspired by fault-tolerant quantum computation
Proceedings of the 2nd conference on Computing frontiers
Multiple-level concatenated coding in embryonics: a dependability analysis
GECCO '05 Proceedings of the 7th annual conference on Genetic and evolutionary computation
A Comparative Evaluation of Designs for Reliable Memory Systems
Journal of Electronic Testing: Theory and Applications
Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m)
Journal of Electronic Testing: Theory and Applications
Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m)
Journal of Electronic Testing: Theory and Applications
An error recoverable structure based on complementary logic and alternating-retry
Journal of Computer Science and Technology
Interactive presentation: Improving the fault tolerance of nanometric PLA designs
Proceedings of the conference on Design, automation and test in Europe
Concurrent error detection in Reed-Solomon encoders and decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bilateral Testing of Nano-scale Fault-Tolerant Circuits
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2m)
Integration, the VLSI Journal
Systematic t-error correcting/all unidirectional error detecting codes with easy encoding/decoding
Computers & Mathematics with Applications
Sliding algorithm for reconfigurable arrays of processors
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Detection of control flow errors using signature and checking instructions
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Designs for dlagnosablllty and reliability in VLSI systems
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Concurrent off-phase built-in self-test of dormant logic
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Design-for-testability and fault-tolerant techniques for FFT processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cost optimization of a class of noncoherent systems
Mathematical and Computer Modelling: An International Journal
Optimal design of hybrid fault-tolerant computer systems
Mathematical and Computer Modelling: An International Journal
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