Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
IEEE Transactions on Computers
IDDQ testing as a component of a test suite: the need for several fault coverage metrics
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Design of the PowerPC 604e microprocessor
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Testing "untestable" faults in three-state circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Compact test sets for industrial circuits
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
IEEE Transactions on Computers
Test Length in a Self-Testing Environment
IEEE Design & Test
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Digital designs, implemented in CMOS technology, haveincreasingly used t&state logic (pass gates) to increaseclock speed. It is also known that tri-state logic baseddesigns have poor testability, as measured by the singlestuck-at fault model, due to the proliferation of "possible-detect" faults. Design For Test techniques that havebeen developed to address testability issues with tri-statelogic designs, often incur hardware and cycle-time over-heads.In this paper, we discuss the effect of one class of"possible-detect" faults and the implicit ability of a testpattern set in detecting such faults on real hardware.