Self-adjusting networks for VLSI simulations
IEEE Transactions on Computers
A Way to Build Efficient Carry-Skip Adders
IEEE Transactions on Computers
VLSI implementation of public-key encryption algorithms
Proceedings on Advances in cryptology---CRYPTO '86
LCS—a leaf cell synthesizer employing formal deduction techniques
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A rule-based circuit representation for automated CMOS design and verification
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
ACM Transactions on Graphics (TOG)
TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAMs
IEEE Transactions on Computers
Performance evaluation of on-chip register and cache organizations
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
A parallel VLSI architecture for unformatted data processing
DPDS '88 Proceedings of the first international symposium on Databases in parallel and distributed systems
Comments on 'Ternary Scan Design for VLSI Testability' by M. Hu and K.C. Smith
IEEE Transactions on Computers
Path-delay constrained floorplanning: a mathematical programming approach for initial placement
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
GRASP: a grammar-based schematic parser
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
CMOS stuck-open fault detection using single test patterns
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip
IEEE Transactions on Computers
The Design of a Microsupercomputer
Computer - Special issue on experimental research in computer architecture
Exploiting parallelism in pattern matching: an information retrieval application
ACM Transactions on Information Systems (TOIS)
IEEE Transactions on Computers
Performance-driven constructive placement
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Performance of Synchronous and Asynchronous Schemes for VLSI Systems
IEEE Transactions on Computers
ELM-A Fast Addition Algorithm Discovered by a Program
IEEE Transactions on Computers
Recurrence equations and the optimization of synchronous logic circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Surveys in combinatorics, 1993
Surveys in combinatorics, 1993
Prime: a timing-driven placement tool using a piecewise linear resistive network approach
DAC '93 Proceedings of the 30th international Design Automation Conference
Simultaneous driver and wire sizing for performance and power optimization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Cost of silicon viewed from VLSI design perspective
DAC '94 Proceedings of the 31st annual Design Automation Conference
A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Routing in a Three-Dimensional Chip
IEEE Transactions on Computers
Pipelined memory shared buffer for VLSI switches
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
A multiple clocking scheme for low power RTL design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
High-level synthesis techniques for reducing the activity of functional units
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Low delay-power product CMOS design using one-hot residue coding
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Optimization of power dissipation and skew sensitivity in clock buffer synthesis
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Quality considerations in delay fault testing
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
VHDL based design methodology for hierarchy and component re-use
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
CAT—caching address tags: a technique for reducing area cost of on-chip caches
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Extracting RTL models from transistor netlists
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Coping with RC(L) interconnect design headaches
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
High-bandwidth address translation for multiple-issue processors
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Developing the VLSI laboratory for the computer architecture course
SIGCSE '96 Proceedings of the twenty-seventh SIGCSE technical symposium on Computer science education
AGENTS: a distributed client-server system for leaf cell generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Basic experimentation on accuracy of power estimation for CMOS VLSI circuits
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Floating body effects in partially-depleted SOI CMOS circuits
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Power comparisons for barrel shifters
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Gate-level synthesis for low-power using new transformations
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses
IEEE Transactions on Computers
Two-ported cache alternatives for superscalar processors
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Journal of Electronic Testing: Theory and Applications
Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Survey of low power techniques for ROMs
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Low power multiplication for FIR filters
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A new 4-2 adder and booth selector for low power MAC unit
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Analytical energy dissipation models for low-power caches
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Dynamic algorithm transformation (DAT) for low-power adaptive signal processing
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Low power data processing by elimination of redundant computations
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A gate resizing technique for high reduction in power consumption
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Increasing memory bandwidth with wide buses: compiler, hardware and performance trade-offs
ICS '97 Proceedings of the 11th international conference on Supercomputing
Tiling design patterns—a case study using the interpreter pattern
Proceedings of the 12th ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications
Complexity-effective superscalar processors
Proceedings of the 24th annual international symposium on Computer architecture
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Formal verification of content addressable memories using symbolic trajectory evaluation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Accurate and efficient macromodel of submicron digital standard cells
DAC '97 Proceedings of the 34th annual Design Automation Conference
Timing analysis based on primitive path delay fault identification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Low power logic synthesis for XOR based circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Analysis of Metastable Operation in a CMOS Dynamic D-Latch
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
C5M—a control logic layout synthesis system for high-performance microprocessors
Proceedings of the 1997 international symposium on Physical design
Minimization of chip size and power consumption of high-speed VLSI buffers
Proceedings of the 1997 international symposium on Physical design
Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags
IEEE Transactions on Computers
Performance optimization of wireless local area networks through VLSI data compression
Wireless Networks - Special issue VLSI in wireless networks
A coarse-grained FPGA architecture for high-performance FIR filtering
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
An LPGA with foldable PLA-style logic blocks
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
DAC '98 Proceedings of the 35th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Arithmetic optimization using carry-save-adders
DAC '98 Proceedings of the 35th annual Design Automation Conference
Monitoring Power Dissipation for Fault Detection
Journal of Electronic Testing: Theory and Applications
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Parallel algorithms for power estimation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Resource widening versus replication: limits and performance-cost trade-off
ICS '98 Proceedings of the 12th international conference on Supercomputing
Double Step Branching CORDIC: A New Algorithm for Fast Sine and Cosine Generation
IEEE Transactions on Computers
Low power logic synthesis under a general delay model
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
SOLO: a generator of efficient layouts from optimized MOS circuit schematics
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An electrical optimizer that considers physical layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An approach to fast hierarchical fault simulation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Quantitative Evaluation of Register Pressure on Software Pipelined Loops
International Journal of Parallel Programming
Efficient Totally Self-Checking Shifter Design
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Fault Modeling and Simulation Using VHDL-AMS
Analog Integrated Circuits and Signal Processing - Special issue: Analog VHDL
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computers
Multiplexer-Based Array Multipliers
IEEE Transactions on Computers
HYPER-LP: a system for power minimization using architectural transformations
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
MOCSYN: multiobjective core-based single-chip system synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automated phase assignment for the synthesis of low power domino circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Mixed-Vth (MVT) CMOS circuit design methodology for low power applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Energy-efficient dynamic circuit design in the presence of crosstalk noise
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Mixed-swing quadrail for low power dual-rail domino logic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
SC2L: a low-power high-performance dynamic differential logic family
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Low power synthesis of dual threshold voltage CMOS VLSI circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
The impact of battery capacity and memory bandwidth on CPU speed-setting: a case study
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
An optimization technique for dual-output domino logic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Inverse polarity techniques for high-speed/low-power multipliers
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
An Effective Built-In Self-Test Scheme for Parallel Multipliers
IEEE Transactions on Computers
DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Software experience with concurrent C and LISP in a distributed system
CSC '88 Proceedings of the 1988 ACM sixteenth annual conference on Computer science
Fast Arithmetic for Public-Key Algorithms in Galois Fields with Composite Exponents
IEEE Transactions on Computers
Vector Transfer by Self-Tested Self-Synchronization for Parallel Systems
IEEE Transactions on Parallel and Distributed Systems
A 32-bit CMOS microprocessor with six-stage pipeline structure
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
A New Class of Depth-Size Optimal Parallel Prefix Circuits
The Journal of Supercomputing
The effect of LUT and cluster size on deep-submicron FPGA performance and density
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Integrated manufacturing and development (IMaD)
SC '99 Proceedings of the 1999 ACM/IEEE conference on Supercomputing
The UniMIN switch architecture for large-scale ATM switches
IEEE/ACM Transactions on Networking (TON)
IEEE Transactions on Computers
A Locally Adaptive Multimode Photodetector Circuit
Analog Integrated Circuits and Signal Processing - Special issue on Learning on Silicon
Critical path analysis using a dynamically bounded delay model
Proceedings of the 37th Annual Design Automation Conference
Modeling and simulation of real defects using fuzzy logic
Proceedings of the 37th Annual Design Automation Conference
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Proceedings of the 27th annual international symposium on Computer architecture
Circuits for wide-window superscalar processors
Proceedings of the 27th annual international symposium on Computer architecture
Interface and cache power exploration for core-based embedded system design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Validation and test generation for oscillatory noise in VLSI interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Optimal allocation of carry-save-adders in arithmetic optimization
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
On the generation of multiplexer circuits for pass transistor logic
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Static timing analysis taking crosstallk into account
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Wire-sizing for delay minimization and ringing control using transmission line model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Fast Implementation of Binary Morphological Operations on Hardware-Efficient Systolic Architectures
Journal of VLSI Signal Processing Systems
High-Speed Booth Encoded Parallel Multiplier Design
IEEE Transactions on Computers - Special issue on computer arithmetic
New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)
IEEE Transactions on Computers
A Low-Power CAM Design for LZ Data Compression
IEEE Transactions on Computers
Scalable Hardware-Algorithms for Binary Prefix Sums
IEEE Transactions on Parallel and Distributed Systems
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
A Low Power 8 × 8 Direct 2-D DCT Chip Design
Journal of VLSI Signal Processing Systems
Constant Number Serial Pipeline Multipliers
Journal of VLSI Signal Processing Systems
False-Path Removal Using Delay Fault Simulation
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
CMOS open defect detection by supply current test
Proceedings of the conference on Design, automation and test in Europe
A graph based algorithm for optimal buffer insertion under accurate delay models
Proceedings of the conference on Design, automation and test in Europe
Switching response modeling of the CMOS inverter for sub-micron devices
Proceedings of the conference on Design, automation and test in Europe
A hybrid approach for core-based system-level power modeling
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Analysis of power-clocked CMOS with application to the design of energy-recovery circuits
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Low-power design of sequential circuits using a quasi-synchronous derived clock
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
An effective low powr design methodology based on interconnect prediction
Proceedings of the 2001 international workshop on System-level interconnect prediction
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits
IEEE Transactions on Computers
A VLSI wrapped wave front arbiter for crossbar switches
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Overcoming wireload model uncertainty during physical design
Proceedings of the 2001 international symposium on Physical design
Optimal spacing and capacitance padding for general clock structures
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A fast and accurate delay estimation method for buffered interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Short circuit power estimation of static CMOS circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
Improved merging of datapath operators using information content and required precision analysis
Proceedings of the 38th annual Design Automation Conference
A true single-phase 8-bit adiabatic multiplier
Proceedings of the 38th annual Design Automation Conference
Two-dimensional position deteciton system with MEMS accelerometer for MOUSE applications
Proceedings of the 38th annual Design Automation Conference
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Low power address encoding using self-organizing lists
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Testing Schemes for FIR Filter Structures
IEEE Transactions on Computers
Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Efficient implementation of a complex ±1 multiplier
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Quantifying and enhancing power awareness of VLSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
ED4I: Error Detection by Diverse Data and Duplicated Instructions
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
Performance analysis of low-power 1-Bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
False path exclusion in delay analysis of RTL structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Detectability Conditions of Full Opens in the Interconnections
Journal of Electronic Testing: Theory and Applications
Compact models for estimating microprocessor frequency and power
Proceedings of the 2002 international symposium on Low power electronics and design
Examining Smart-Card Security under the Threat of Power Analysis Attacks
IEEE Transactions on Computers
Optimum multiuser detection for CDMA systems using the mean field annealing neural network
Hardware implementation of intelligent systems
An adaptive low-power transmission scheme for on-chip networks
Proceedings of the 15th international symposium on System Synthesis
Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits
Journal of VLSI Signal Processing Systems
Analysis of High-Performance Flip-Flops for Submicron Mixed-Signal Applications
Analog Integrated Circuits and Signal Processing
Silicon physical random functions
Proceedings of the 9th ACM conference on Computer and communications security
Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
A Low-Power Block-Matching Cell for VideoCompression
Analog Integrated Circuits and Signal Processing
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells
Journal of VLSI Signal Processing Systems
Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers
Journal of VLSI Signal Processing Systems
Behavior-to-placed RTL synthesis with performance-driven placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
O2 ABA: a novel high-performance predictable circuit architecture for the deep submicron era
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient FFT network testing and diagnosis schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Constructing H4, a Fast Depth-Size Optimal Parallel Prefix Circuit
The Journal of Supercomputing
An Integrated Framework for the Design and Optimization of SOC Test Solutions
Journal of Electronic Testing: Theory and Applications
Built-In Self-Test of a CMOS ALU
IEEE Design & Test
Design Synthesis and Silicon Compilation
IEEE Design & Test
Designing in Power-Down Test Circuits
IEEE Design & Test
PowerPC 603, A Microprocessor for Portable Computers
IEEE Design & Test
Saving Power by Synthesizing Gated Clocks for Sequential Circuits
IEEE Design & Test
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems
IEEE Design & Test
Real-Time Current Testing for A/D Converters
IEEE Design & Test
FPGA Adders: Performance Evaluation and Optimal Design
IEEE Design & Test
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
Fault-Secure Parity Prediction Booth Multipliers
IEEE Design & Test
Random-Access Data Storage Components in Customized Architectures
IEEE Design & Test
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
IEEE Micro
VLSI Algorithms, Architectures, and Implementation of a Versatile GF(2m) Processor
IEEE Transactions on Computers
IEEE Transactions on Computers
Systematic Design of Pipelined Recursive Filters
IEEE Transactions on Computers
IEEE Transactions on Computers
A Fault-Tolerant GEQRNS Processing Element for Linear Systolic Array DSP Applications
IEEE Transactions on Computers
Efficient Totally Self-Checking Checkers for a Class of Borden Codes
IEEE Transactions on Computers
On Hardware for Computing Exponential and Trigonometric Functions
IEEE Transactions on Computers
Topics in the theory of DNA computing
Theoretical Computer Science - Natural computing
On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation
Journal of Systems Architecture: the EUROMICRO Journal
A Reconfigurable Content Addressable Memory
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Finite Digital Synchronous Circuits Are Characterized by 2-Algebraic Truth Tables
ASIAN '00 Proceedings of the 6th Asian Computing Science Conference on Advances in Computing Science
A Power-Sum Systolic Architecture in GF(2m)
ICOIN '02 Revised Papers from the International Conference on Information Networking, Wireless Communications Technologies and Network Applications-Part II
Physical Design of CMOS Chips in Six Easy Steps
SOFSEM '00 Proceedings of the 27th Conference on Current Trends in Theory and Practice of Informatics
Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Output Waveform Evaluation of Basic Pass Transistor Structure
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
A Fault Tolerant Approach to Microprocessor Design
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Multiple-Wordlength Resource Binding
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Randomized Addition-Subtraction Chains as a Countermeasure against Power Attacks
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
A hybrid adiabatic content addressable memory for ultra low-power applications
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A decoupling technique for CMOS strong-coupled structures
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Computer
A low-power adder operating on effective dynamic data ranges
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new 2-D systolic digital filter architecture without global broadcast
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A technique for improving dual-output domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ECO algorithms for removing overlaps between power rails and signal wires
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Standby power optimization via transistor sizing and dual threshold voltage assignment
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An effective BIST design for PLA
ATS '95 Proceedings of the 4th Asian Test Symposium
Serial transistor network modeling for bridging fault simulation
ATS '95 Proceedings of the 4th Asian Test Symposium
Asynchronous circuits based on multiple localised current-sensing completion detection
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Energy and Performance Models for Clocked and Asynchronous Communication
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
A Combined Pairing and Chaining Algorithm for CMOS Layout Generation
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Design and selection of buffers for minimum power-delay product
EDTC '96 Proceedings of the 1996 European conference on Design and Test
An Efficient Algorithm for Signal Flow Determination in Digital CMOS VLSI
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Shaping a VLSI Wire to Minimize Elmore Delay
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Inductance Analysis of On-Chip Interconnects
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists
Formal Methods in System Design
Multi-way partitioning of VLSI circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Low-Power Design by Hazard Filtering
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
An Asynchronous Morphological Processor for Multi-Media Applications
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Shift Switching with Domino Logic: Asynchronous VLSI Comparator Schemes
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Methodology for Accurate Modeling of Energy Dissipation in Array Structures
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Analysis of Ground Bounce in Deep Sub-Micron Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Technique For Testing A Very High Speed Mixed Signal Read Channel Design
ITC '00 Proceedings of the 2000 IEEE International Test Conference
AN IDDQ SENSOR CIRCUIT FOR LOW-VOLTAGE ICS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
DESIGN OF CACHE TEST HARDWARE ON THE HP PA8500
ITC '97 Proceedings of the 1997 IEEE International Test Conference
How Seriously Do You Take Possible-Detect Faults?
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On Testability of Multiple Precharged Domino Logic
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Position Statement: Increasing Test Coverage in a VLSI Design Course
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Systolic architectures for inversion/division using AB2 circuits in GF(2m)
Integration, the VLSI Journal
High-performance FIR filter design based on sharing multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A circuit level fault model for resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Architectural techniques for accelerating subword permutations with repetitions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
An efficient two-dimensional compaction algorithm for VLSI symbolic layout
EURO-DAC '90 Proceedings of the conference on European design automation
Transmission gate delay models for circuit optimization
EURO-DAC '90 Proceedings of the conference on European design automation
Cell based performance optimization of combinational circuits
EURO-DAC '90 Proceedings of the conference on European design automation
A dynamic programming approach to the power supply net sizing problem
EURO-DAC '90 Proceedings of the conference on European design automation
Power efficient encoding techniques for off-chip data buses
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Journal of Electronic Testing: Theory and Applications
Delay-based circuit authentication and applications
Proceedings of the 2003 ACM symposium on Applied computing
Z4: a new depth-size optimal parallel prefix circuit with small depth
Neural, Parallel & Scientific Computations
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Analysis of blocking dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive low-power address encoding techniques using self-organizing lists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Integration, the VLSI Journal
Synthesis of integer multipliers in sum of pseudoproducts form
Integration, the VLSI Journal
Power minimization algorithms for LUT-based FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the conference on Design, automation and test in Europe - Volume 3
A new approach to constructing optimal parallel prefix circuits with small depth
Journal of Parallel and Distributed Computing
Clock network sizing via sequential linear programming with time-domain analysis
Proceedings of the 2004 international symposium on Physical design
LECTOR: a technique for leakage reduction in CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Complex ±1 Multiplier Based on Signed-Binary Transformations
Journal of VLSI Signal Processing Systems
A Multiplierless 2-D Convolver Chip for Real-Time Image Processing
Journal of VLSI Signal Processing Systems
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
PACE: A New Approach to Dynamic Voltage Scaling
IEEE Transactions on Computers
Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs
Proceedings of the 31st annual international symposium on Computer architecture
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Weibull Based Analytical Waveform Model
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Equivalent Waveform Propagation for Static Timing Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fine-grain real-time reconfigurable pipelining
IBM Journal of Research and Development
ACM Transactions on Embedded Computing Systems (TECS)
Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
LPRAM: a low power DRAM with testability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A loop accelerator for low power embedded VLIW processors
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Analytical models for leakage power estimation of memory array structures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Practical PACE for embedded systems
Proceedings of the 4th ACM international conference on Embedded software
A low power architecture for embedded perception
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Low Cost and High Speed Embedded Two-Rail Code Checker
IEEE Transactions on Computers
Systematic Analysis of Active Clock Deskewing Systems Using Control Theory
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Modeling Custom Digital Circuits for Test
Journal of Electronic Testing: Theory and Applications
Multithreshold voltage low-swing/low-voltage techniques in logic gates
Integration, the VLSI Journal
High-speed systolic architectures for finite field inversion
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Ultralow-power adiabatic circuit semi-custom design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Skewed caches from a low-power perspective
Proceedings of the 2nd conference on Computing frontiers
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Proceedings of the 42nd annual Design Automation Conference
A greedy strategy for detecting negative cost cycles in networks
Future Generation Computer Systems - Special issue: High-speed networks and services for data-intensive grids: The DataTAG project
A fast, energy-efficient z-comparator
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
Encyclopedia of Computer Science
Self-Checking Voter for High Speed TMR Systems
Journal of Electronic Testing: Theory and Applications
An alternative logic approach to implement high-speed low-power full adder cells
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
Minimizing expected energy in real-time embedded systems
Proceedings of the 5th ACM international conference on Embedded software
Power complexity of multiplexer-based optoelectronic crossbar switches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A digit-serial multiplier for finite field GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analytical modeling of crosstalk noise waveforms using Weibull function
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Modeling unbuffered latches for timing analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Processor Array Architectures for Deep Packet Classification
IEEE Transactions on Parallel and Distributed Systems
Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Efficient LUT-based FPGA technology mapping for power minimization
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Robust high-performance low-power carry select adder
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Arbitrary long digit integer sorter HW/SW co-design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Analysis of buffered hybrid structured clock networks
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Achieving continuous VT performance in a dual VT process
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Stability analysis of active clock deskewing systems using a control theoretic approach
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Transistor-Level Optimization of Supergates
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
The circuit design of the synergistic processor element of a CELL processor
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Reasoning about synchronization in GALS systems
Formal Methods in System Design
Origins and motivations for design rules in QCA
Nano, quantum and molecular computing
A VLSI architecture for watermarking in a secure still digital camera (S2DC) design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
A PLA based asynchronous micropipelining approach for subthreshold circuit design
Proceedings of the 43rd annual Design Automation Conference
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel multiple-valued CMOS flip-flop employing multiple-valued clock
Journal of Computer Science and Technology
Formal Methods in System Design
Operating System Modifications for Task-Based Speed and Voltage
Proceedings of the 1st international conference on Mobile systems, applications and services
Mixed Full Adder topologies for high-performance low-power arithmetic circuits
Microelectronics Journal
Emulating switch-level models of CMOS circuits
Microelectronic Engineering
A path based modeling approach for dynamic power estimation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Lowering power in an experimental RISC processor
Microprocessors & Microsystems
A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture
IEEE Transactions on Computers
High performance low power CMOS dynamic logic for arithmetic circuits
Microelectronics Journal
Analytical Model for the CMOS Short-Circuit Power Dissipation
Integrated Computer-Aided Engineering
Controlled physical random functions and applications
ACM Transactions on Information and System Security (TISSEC)
Journal of Electronic Testing: Theory and Applications
Design of a low-power VLSI macrocell for nonlinear adaptive video noise reduction
EURASIP Journal on Applied Signal Processing
A unified practical approach to stochastic DVS scheduling
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
Minimizing expected energy consumption in real-time systems through dynamic voltage scaling
ACM Transactions on Computer Systems (TOCS)
IEEE Transactions on Dependable and Secure Computing
A new approach to power estimation and reduction in CMOS digital circuits
Integration, the VLSI Journal
A BIST TPG for low power dissipation and high fault coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analog Integrated Circuits and Signal Processing
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A new low energy BIST using a statistical code
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A robust, fast pulsed flip-flop design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy recovery strategy for low power CMOS circuits design
ICECS'03 Proceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing
Designing and implementing malicious hardware
LEET'08 Proceedings of the 1st Usenix Workshop on Large-Scale Exploits and Emergent Threats
Slack allocation based co-synthesis and optimization of bus and memory architectures for MPSoCs
Proceedings of the conference on Design, automation and test in Europe
A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption
Journal of Signal Processing Systems
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Two new low-power Full Adders based on majority-not gates
Microelectronics Journal
Closed-loop modeling of power and temperature profiles of FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Fast problem-size-independent parallel prefix circuits
Journal of Parallel and Distributed Computing
Safe clocking for the setup and hold timing constraints in datapath synthesis
Proceedings of the 19th ACM Great Lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sleepy stack leakage reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High speed gate level synchronous full adder designs
WSEAS Transactions on Circuits and Systems
A novel low-power full-adder cell for low voltage
Integration, the VLSI Journal
A delay improved gate level full adder design
ECC'09 Proceedings of the 3rd international conference on European computing conference
A predictive dynamic output buffer reconfiguration (PDOBR) architecture for ATM networks
Computer Communications
A secure digital camera architecture for integrated real-time digital rights management
Journal of Systems Architecture: the EUROMICRO Journal
Custom circuit design as a driver of microprocessor performance
IBM Journal of Research and Development
Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2m)
Integration, the VLSI Journal
Coscheduling of processor voltage and control task period for energy-efficient control systems
ACM Transactions on Embedded Computing Systems (TECS)
Partitioning and ordering of CMOS circuits for switch level analysis
Integration, the VLSI Journal
iCOACH: A circuit optimization aid for CMOS high-performance circuits
Integration, the VLSI Journal
High-speed systolic architectures for finite field inversion
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
IEEE Transactions on Wireless Communications
FleXilicon architecture and its VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A low power gate level full adder module
ASMCSS'09 Proceedings of the 3rd International Conference on Applied Mathematics, Simulation, Modelling, Circuits, Systems and Signals
Proceedings of the International Conference and Workshop on Emerging Trends in Technology
Fast arithmetic architectures for public-key algorithms over Galois fields GF((2n)m)
EUROCRYPT'97 Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques
A compact and fast division architecture for a finite field GF(2m)
ICCSA'03 Proceedings of the 2003 international conference on Computational science and its applications: PartI
AOP-based high-level power estimation in SystemC
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer
Journal of Electronic Testing: Theory and Applications
Built-in sensor for signal integrity faults in digital interconnect signals
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient architecture for accumulator-based test generation of SIC pairs
Microelectronics Journal
FPGA vernier digital-to-time converter with 1.58 ps resolution and 59.3 minutes operation range
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A novel CMOS 1-bit 8T full adder cell
WSEAS TRANSACTIONS on SYSTEMS
An efficient low-power buffer insertion with time and area constraints
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
Gate-sizing-based single Vdd test for bridge defects in multivoltage designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test cost reduction for multiple-voltage designs with bridge defects through gate-sizing
Proceedings of the Conference on Design, Automation and Test in Europe
Parallel pattern fast fault simulation for three-state circuits and bidirectional I/O
ITC'94 Proceedings of the 1994 international conference on Test
RTRAM: reconfigurable and testable multi-bit RAM design
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A systolic VLSI architecture for multi-dimensional transforms
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
A micropower low-voltage multiplier with reduced spurious switching
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power minimization for dynamic PLAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sequence-switch coding for low-power data transmission
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CONTROL'05 Proceedings of the 2005 WSEAS international conference on Dynamical systems and control
CMOS full-adders for energy-efficient arithmetic applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New low-power tristate circuits in positive feedback source-coupled logic
Journal of Electrical and Computer Engineering
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Design of variable input delay gates for low dynamic power circuits
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Concurrent error detection architectures for field multiplication using gaussian normal basis
ISPEC'10 Proceedings of the 6th international conference on Information Security Practice and Experience
Low-power, high-performance TTA processor for 1024-point fast fourier transform
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Parceling the butterfly and the batcher sorting network
Theoretical Computer Science
Quasi-static fault-tolerant scheduling schemes for energy-efficient hard real-time systems
Journal of Systems and Software
VLSI implementation of a distributed algorithm for fault-tolerant clock generation
Journal of Electrical and Computer Engineering - Special issue on Clock/Frequency Generation Circuits and Systems
9T full adder design in subthreshold region
VLSI Design
Static power consumption in CMOS gates using independent bodies
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Design of a low-power embedded processor architecture using asynchronous function units
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Design of 9-transistor single bit full adder
Proceedings of the Second International Conference on Computational Science, Engineering and Information Technology
A low-power globally synchronous locally asynchronous FFT processor
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems
Proceedings of the Conference on Design, Automation and Test in Europe
Hardware support for accurate per-task energy metering in multicore systems
ACM Transactions on Architecture and Code Optimization (TACO)
Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style
Integration, the VLSI Journal
A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages
International Journal of High Performance Systems Architecture
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits
Journal of Electronic Testing: Theory and Applications
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