Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
An "effective" capacitance based delay metric for RC interconnect
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Accurate CMOS bridge fault modeling with neural network-based VHDL saboteurs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
On the capability of delay tests to detect bridges and opens
ATS '97 Proceedings of the 6th Asian Test Symposium
Analyzing Crosstalk in the Presence of Weak Bridge Defects
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
The concept of resistance interval: a new parametric model for realistic resistive bridging fault
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Delay Testing Considering Power Supply Noise Effects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
CodSim—A Combined Delay Fault Simulator
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Testing for Resistive Shorts in FPGA Interconnects
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Automatic Test Pattern Generation for Resistive Bridging Faults
Journal of Electronic Testing: Theory and Applications
Stochastic formulation of SPICE-type electronic circuit simulation with polynomial chaos
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Resistive bridging fault simulation of industrial circuits
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Delay faults are an increasingly important test challenge. Modeling bridge faults as delay faults helps delay tests to detect more bridge faults. Traditional bridge fault models are incomplete because these models only model the logic faults or these models are not efficient to use in delay tests for large circuits. In this article, we propose a physically realistic yet economical resistive bridge fault model to model delay faults as well as logic faults. An accurate yet simple delay calculation method is proposed. We also enumerate all possible fault behaviors and present the relationship between input patterns and output behaviors, which is useful in ATPG. Our fault simulation results show the benefit of at-speed tests.