E-PROOFS: a CMOS bridging fault simulator
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Detection of Defects Using Fault Model Oriented Test Sequences
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
New Techniques for Deterministic Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
Accurate Fault Modeling and Fault Simulation of Resistive Bridges
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages
Proceedings of the IEEE International Test Conference on Test and Design Validity
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
BART: A Bridging Fault Test Generation for Sequential Circuits
Proceedings of the IEEE International Test Conference
Bridging fault coverage improvement by power supply control
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
PROBE: A PPSFP Simulator for Resistive Bridging Faults
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Precise Test Generation for Resistive Bridging Faults of CMOS Combinational Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems
ATS '01 Proceedings of the 10th Asian Test Symposium
The concept of resistance interval: a new parametric model for realistic resistive bridging fault
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Modeling Feedback Bridging Faults With Non-Zero Resistance
ETW '03 Proceedings of the 8th IEEE European Test Workshop
A circuit level fault model for resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
SPIRIT: a highly robust combinational test generation algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Resistive bridging fault simulation of industrial circuits
Proceedings of the conference on Design, automation and test in Europe
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Gate-sizing-based single Vdd test for bridge defects in multivoltage designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test cost reduction for multiple-voltage designs with bridge defects through gate-sizing
Proceedings of the Conference on Design, Automation and Test in Europe
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An ATPG for resistive bridging faults in combinational or full-scan circuits is proposed. It combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced so far, it can handle static effects of arbitrary non-feedback bridges between two nodes, including ones detectable at higher bridge resistance and undetectable at lower resistance, and faults requiring more than one vector for detection. The developed tool is applied to ISCAS circuits, and a higher efficiency compared with other resistive bridging fault as well as stuck-at ATPG is reported. Information required for accurate resistive bridging fault simulation is obtained as a by-product.