Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Detection of Defects Using Fault Model Oriented Test Sequences
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Test point insertion based on path tracing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Bridging fault coverage improvement by power supply control
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Precise Test Generation for Resistive Bridging Faults of CMOS Combinational Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
An Unified Fault Model and Test Generation Procedure for Interconnect Opens and Bridges
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Automatic Test Pattern Generation for Resistive Bridging Faults
Journal of Electronic Testing: Theory and Applications
Design-for-testability for path delay faults in large combinational circuits using test points
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simulating Resistive-Bridging and Stuck-At Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bridging Fault Test Method With Adaptive Power Management Awareness
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% defect coverage; however switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes an effective Gate Sizing technique for reducing test cost of multi-Vdd designs with bridge defects. Using synthesized ISCAS benchmarks and a parametric fault model, experimental results show that for all the circuits, the proposed technique achieves 100% defect coverage at a single Vdd setting; in addition it has a lower overhead than the recently proposed Test Point Insertion technique in terms of timing, area and power.