E-PROOFS: a CMOS bridging fault simulator
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Bridge fault simulation strategies for CMOS integrated circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Logic Testing of Bridging Faults in CMOS Integrated Circuits
IEEE Transactions on Computers
IDDQ testing: state of the art and future trends
Integration, the VLSI Journal - Special issue on VLSI testing
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
An Accurate Bridging Fault Test Pattern Generator
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
BART: A Bridging Fault Test Generation for Sequential Circuits
Proceedings of the IEEE International Test Conference
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Process-tolerant test with energy consumption ratio
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Fast and Accurate CMOS Bridging Fault Simulation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Voting model based diagnosis of bridging faults in combinational circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
The concept of resistance interval: a new parametric model for realistic resistive bridging fault
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A Comparison of Bridging Fault Simulation Methods
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Histogram Based Procedure for Current Testing of Active Defects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Statistical Threshold Formulation For Dynamic Idd Test
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Transient Current Testing of 0.25 µm CMOS Devices
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An efficient CMOS bridging fault simulator: with SPICE accuracy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits
Journal of Electronic Testing: Theory and Applications
Modeling Feedback Bridging Faults with Non-Zero Resistance
Journal of Electronic Testing: Theory and Applications
Automatic Test Pattern Generation for Resistive Bridging Faults
Journal of Electronic Testing: Theory and Applications
Fault diagnosis of physical defects using unknown behavior model
Journal of Computer Science and Technology
How Many Test Vectors We Need to Detect a Bridging Fault?
Journal of Electronic Testing: Theory and Applications
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Gate-sizing-based single Vdd test for bridge defects in multivoltage designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test cost reduction for multiple-voltage designs with bridge defects through gate-sizing
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper we propose a new method to detect resistive bridging faults by logic testing considering fault effects that depend on the gate threshold voltage and gateinput vectors. First we show that some bridging faultscan be missed to be detected by the traditional test generation method which generates 0 and 1 at the bridgingsignal lines, and then propose a novel method to detectresistive bridging faults by logic testing method, whichis complete in the sense that the undetectable resistivebridging fault by this algorithm gives correct result inlogical operation. A heuristic method using random pat-tern has also been proposed for experimental purpose. Inorder to show the effectiveness of the proposed methodsome experimental results for benchmark circuits havebeen shown.