An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
IC Failure Analysis Tools and Techniques - Macig, Mystery, and Science
Proceedings of the IEEE International Test Conference on Test and Design Validity
IDDQ and AC Scan: The War Against Unmodelled Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
An Overview of CMOS VLSI Failure Analysis and the Importance of Test and Diagnostics
Proceedings of the IEEE International Test Conference on Test and Design Validity
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment
Proceedings of the IEEE International Test Conference
Application and Analysis of IDDQ Diagnostic Software
Proceedings of the IEEE International Test Conference
Current Signatures: Application
Proceedings of the IEEE International Test Conference
Signature Analysis for IC Diagnosis and Failure Analysis
Proceedings of the IEEE International Test Conference
The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Current signatures for integrated circuit test strategy advisor
Current signatures for integrated circuit test strategy advisor
Defect classes - an overdue paradigm for CMOS IC testing
ITC'94 Proceedings of the 1994 international conference on Test
Extraction and simulation of realistic CMOS faults using inductive fault analysis
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults
IEEE Transactions on Computers
Current Testing Procedure for Deep Submicron Devices
Journal of Electronic Testing: Theory and Applications
Studies of the SEMATECH IDDq test data
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
Current Testing Procedure for Deep Submicron Devices
ETW '00 Proceedings of the IEEE European Test Workshop
Comparison of Defect Detection Capabilities of Current-Based and Voltage-Based Test Methods
ETW '00 Proceedings of the IEEE European Test Workshop
Comparison of Defect Detection Capabilities of Current-Based and Voltage-Based Test Methods
ETW '00 Proceedings of the IEEE European Test Workshop
Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Precise Test Generation for Resistive Bridging Faults of CMOS Combinational Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Empirical Study on the Effects of Test Type Ordering on
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Increasing the IDDQ Test Resolution Using Current Prediction
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Logic Mapping on a Microprocessor
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Practical Built-In Current Sensor for IDDQ Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Study of Test Quality/Tester Scan Memory Trade-offs Using the SEMATECH Test Methods Data
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Eliminating the Ouija® Board: Automatic Thresholds and Probabilistic IDDQ Diagnosis
ITC '99 Proceedings of the 1999 IEEE International Test Conference
High-Frequency, At-Speed Scan Testing
IEEE Design & Test
Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains
IEEE Transactions on Computers
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Multi-temperature testing for core-based system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Diagnosis of single stuck-at faults and multiple timing faults in scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level impact of chip-level failure mechanisms and screens
Proceedings of the International Conference on Computer-Aided Design
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SEMATECH has sponsored a "Test Method Evaluation"study to understand the trade-offs among the most commontest methodologies used in the industry[1,2]. This paper presentsthe results of the failure analysis portion of thatproject. The testing, reliability stressing, characterization,fault diagnosis and physical analysis results are presentedfor 25 devices including "IDDq-only" failures and "delaytest-only" failures.