Discontinuities Driven by a Billion Connected Machines
IEEE Design & Test
IDDQ and AC Scan: The War Against Unmodelled Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
Test Strategy Sensitivity to Defect Parameters
Proceedings of the IEEE International Test Conference
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Testing for bridging faults (shorts) in CMOS circuits
DAC '83 Proceedings of the 20th Design Automation Conference
Transient Current Testing Based on Current (Charge) Integration
IDDQ '98 Proceedings of the IEEE International Workshop on IDDQ Testing
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Transient Current Testing of 0.25 µm CMOS Devices
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test Considerations for Gate Oxide Shorts in CMOS ICs
IEEE Design & Test
Defect classes - an overdue paradigm for CMOS IC testing
ITC'94 Proceedings of the 1994 international conference on Test
Extraction and simulation of realistic CMOS faults using inductive fault analysis
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Defect level evaluation in an IC design environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The Future of Delta IDDQ Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testing for Resistive Opens and Stuck Opens
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Nanometer Design: What are the Requirements for Manufacturing Test?
Proceedings of the conference on Design, automation and test in Europe - Volume 2
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Ramp Voltage Testing for Detecting Interconnect Open Faults
IEICE - Transactions on Information and Systems
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The industrial default to test random logic is based on stuck-at fault test patterns applied via scan-chains. This test-method can be described as static voltage testing. A second well-known method is I DDQ testing, which can be described as static current testing. This second method is especially suited for detecting resistive shorts. For deep sub-micron technologies, new defect mechanisms start to become important. Especially, opens are a much-feared type of defect since static test methods are less suited to detect these defects. Dynamic test methods such as delay-fault testing and transient current testing could fill this gap in the test suite. The paper gives an overview of the aforementioned test-methods including some of the new current-based test methods necessary for deep submicron technologies and their defect detection capabilities.