IDDQ and AC Scan: The War Against Unmodelled Defects

Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of test subsequences

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

An approach to test compaction for scan circuits that enhances at-speed testing

Proceedings of the 38th annual Design Automation Conference

Estimating the Economic Benefits of DFT

IEEE Design & Test

Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times

IEEE Transactions on Computers

A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set

IEEE Transactions on Computers

Performance Comparison of VLV, ULV, and ECR Tests

Journal of Electronic Testing: Theory and Applications

Estimation of defect-free IDDQ in submicron circuits using switch level simulation

ITC '98 Proceedings of the 1998 IEEE International Test Conference

High volume microprocessor test escapes, an analysis of defects our tests are missing

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment

ITC '98 Proceedings of the 1998 IEEE International Test Conference

CMOS IC reliability indicators and burn-in economics

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Comparison of Defect Detection Capabilities of Current-Based and Voltage-Based Test Methods

ETW '00 Proceedings of the IEEE European Test Workshop

Comparison of Defect Detection Capabilities of Current-Based and Voltage-Based Test Methods

ETW '00 Proceedings of the IEEE European Test Workshop

A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

6.3 Experimental Results for IDDQ and VLV Testing

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Deception by Design: Fooling Ourselves with Gate-level Models

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Comparing Functional and Structural Tests

ITC '00 Proceedings of the 2000 IEEE International Test Conference

An Empirical Study on the Effects of Test Type Ordering on

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Logic Mapping on a Microprocessor

ITC '00 Proceedings of the 2000 IEEE International Test Conference

On Improving the Stuck-at Fault Coverage of Functional Test Sequences by Using Limited-Scan Operations

ITC '01 Proceedings of the 2001 IEEE International Test Conference

A Practical Built-In Current Sensor for IDDQ Testing

ITC '01 Proceedings of the 2001 IEEE International Test Conference

AN IDDQ SENSOR CIRCUIT FOR LOW-VOLTAGE ICS

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Intrinsic Leakage in Low Power Deep Submicron CMOS ICs

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Experiences with Implementation of IDDQ Test for Identification and Automotive Products

ITC '97 Proceedings of the 1997 IEEE International Test Conference

On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

1998 ITC Best Paper: Failure Analysis of Timing and IDDQ-only Failures from the SEMATECH Test Methods Experiment

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation

ITC '99 Proceedings of the 1999 IEEE International Test Conference

AC Scan Path Selection for Physical Debugging

IEEE Design & Test

Compact Dictionaries for Fault Diagnosis in Scan-BIST

IEEE Transactions on Computers

Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests

IEEE Transactions on Computers

Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs

IEEE Transactions on Computers

Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

Double-single stuck-at faults: a delay fault model for synchronous sequential circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

TOV: sequential test generation by ordering of test vectors

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power

Journal of Electronic Testing: Theory and Applications

Criteria for static current estimation: how good are they? an approach incorporating IC quality requirements

SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design

Reducing the storage requirements of a test sequence by using a background vector

Proceedings of the Conference on Design, Automation and Test in Europe

Built-in generation of multicycle functional broadside tests with observation points

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Design-for-testability for multi-cycle broadside tests by holding of state variables

ACM Transactions on Design Automation of Electronic Systems (TODAES)