Randomized rounding: a technique for provably good algorithms and algorithmic proofs
Combinatorica - Theory of Computing
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
IDDQ and AC Scan: The War Against Unmodelled Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
Inserting Test Points to Control Peak Power During Scan Testing
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption
ATS '99 Proceedings of the 8th Asian Test Symposium
An Input Control Technique for Power Reduction in Scan Circuits During Test Application
ATS '99 Proceedings of the 8th Asian Test Symposium
Peak-power reduction for multiple-scan circuits during test application
ATS '00 Proceedings of the 9th Asian Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimization Trade-offs for Vector Volume and Test Power
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Scan-Based Transition Fault Testing " Implementation and Low Cost Test Challenges
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Scan Power Reduction Through Test Data Transition Frequency Analysis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Reducing Average and Peak Test Power Through Scan Chain Modification
Journal of Electronic Testing: Theory and Applications
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores
ATS '01 Proceedings of the 10th Asian Test Symposium
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Reducing Power Dissipation during Test Using Scan Chain Disable
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Test Power Reduction through Minimization of Scan Chain Transitions
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test Vector Modification for Power Reduction during Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Controlling Peak Power During Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
High-Frequency, At-Speed Scan Testing
IEEE Design & Test
Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
IEEE Design & Test
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
At-Speed Transition Fault Testing With Low Speed Scan Enable
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
On Low-Capture-Power Test Generation for Scan Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Reduction of Instantaneous Power by Ripple Scan Clocking
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Jump Scan: A DFT Technique for Low Power Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Low Cost Launch-on-Shift Delay Test with Slow Scan Enable
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Dynamic scan chain partitioning for reducing peak shift power during test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Scan-based testing of integrated circuits results in significant switching activity during the shift operations, dissipating excessive power levels. When such levels are beyond the peak power level under which the chip can functionally operate at, it may lead to an unexpected behavior of the design, resulting in a yield loss. One of the most effective solutions to reduce peak shift power is to partition the scan chains into multiple groups, wherein a single group is active at any time instance within a shift cycle. The partitioning of the chains into groups can be performed statically, i.e., per test set, or dynamically, i.e., per test pattern. In this work, we address the application of dynamic scan chain partitioning for reducing peak shift power. First, we address the application of dynamic partitioning to test delay faults in at-speed test techniques. Then, we formulate the scan chain partitioning problem via Integer Linear Programming (ILP), in order to evenly distribute the transitions produced by any pattern over multiple time instances within the shift cycle, maximally reducing the peak shift power. Finally, we evaluate the power reduction benefit of dynamic partitioning through an extensive set of experiments using different scan configurations and test set characteristics of benchmark circuits as well as industrial designs. The results indicate that dynamic partitioning provides significant reduction to peak shift power over static partitioning methods, and that the benefit is accentuated in scan architectures with fewer scan chains, test sets with more don't care bits, and designs with larger variances of weight differences for transitions in the scan cells.