Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Inserting Test Points to Control Peak Power During Scan Testing
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Gate leakage reduction for scaled devices using transistor stacking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An automatic test pattern generator for minimizing switching activity during scan testing activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations
Journal of Electronic Testing: Theory and Applications
Efficient partial scan cell gating for low-power scan-based testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
Customizing pattern set for test power reduction via improved X-identification and reordering
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
Journal of Electronic Testing: Theory and Applications
X-filling for simultaneous shift- and capture-power reduction in at-speed scan-based testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integration, the VLSI Journal
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Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in future technologies the static portion of power dissipation will outreach the dynamic portion. This paper proposes an efficient technique to reduce both dynamic and static power dissipation in scan structures. Scan cell outputs which are not on the critical path(s) are multiplexed to fixed values during scan mode. These constant values and primary inputs are selected such that the transitions occurred on non-multiplexed scan cells are suppressed and the leakage current during scan mode is decreased. A method for finding these vectors is also proposed. Effectiveness of this technique is proved by experiments performed on ISCAS89 benchmark circuits.