A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Dynamic search-space pruning techniques in path sensitization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Small Test Generator for Large Designs
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Robust Search Algorithms for Test Pattern Generation
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
SMART And FAST: Test Generation for VLSI Scan-Design Circuits
IEEE Design & Test
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
The Complexity of Fault Detection Problems for Combinational Logic Circuits
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Combinational test generation using satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Hybrid Fault Simulation for Synchronous Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Low-cost sequential ATPG with clock-control DFT
Proceedings of the 39th annual Design Automation Conference
Deterministic test pattern generation techniques for sequential circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Compact two-pattern test set generation for combinational and full scan circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Conflict driven techniques for improving deterministic test pattern generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Implication and Evaluation Techniques for Proving Fault Equivalence
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Challenges and directions for testing IC
Integration, the VLSI Journal
Efficient Preimage Computation Using A Novel Success-Driven ATPG
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Journal of Electronic Testing: Theory and Applications
Incremental Design Debugging in a Logic Synthesis Environment
Journal of Electronic Testing: Theory and Applications
ATPG-based preimage computation: efficient search space pruning with ZBDD
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Scan test planning for power reduction
Proceedings of the 44th annual Design Automation Conference
Scan chain clustering for test power reduction
Proceedings of the 45th annual Design Automation Conference
Novel probabilistic combinational equivalence checking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electronic Testing: Theory and Applications
Relative generic computational forensic techniques
IH'04 Proceedings of the 6th international conference on Information Hiding
| Hi-index | 0.00 |
This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. This is achieved by finding more necessary signal line assignments, by detecting conflicts earlier, and by avoiding unnecessary work during test generation. We have incorporated these techniques into an ATPG system for combinational circuits, called ATOM. The performance results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits demonstrated the effectiveness of these techniques on the test generation performance.