Spectral K-way ratio-cut partitioning and clustering
DAC '93 Proceedings of the 30th international Design Automation Conference
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Test and Reliability: Partners in IC Manufacturing, Part 1
IEEE Design & Test
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Integrating Scan into Hierarchical Synthesis Methodologies
Proceedings of the IEEE International Test Conference on Test and Design Validity
A new approach to scan chain reordering using physical design information
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A layout-based approach for ordering scan chain flip-flops
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Reducing Power Dissipation during Test Using Scan Chain Disable
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Test Vector Modification for Power Reduction during Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Power-Conscious Test Synthesis and Scheduling
IEEE Design & Test
Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Low Power Test Data Compression Based on LFSR Reseeding
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
X-Masking During Logic BIST and Its Impact on Defect Coverage
ITC '04 Proceedings of the International Test Conference on International Test Conference
Scan test planning for power reduction
Proceedings of the 44th annual Design Automation Conference
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A power-effective scan architecture using scan flip-flops clustering and post-generation filling
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Scan power reduction in linear test data compression scheme
Proceedings of the 2009 International Conference on Computer-Aided Design
On reducing test power and test volume by selective pattern compression schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scan power reduction for linear test compression schemes through seed selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Incremental multiple-scan chain ordering for ECO flip-flop insertion
Proceedings of the International Conference on Computer-Aided Design
Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction
Journal of Electronic Testing: Theory and Applications
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An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-flops into scan chains, which determines how many chains can be deactivated per pattern. In this paper, a new method to cluster flip-flops into scan chains is presented, which minimizes the power consumption during test. It is not dependent on a test set and can improve the performance of any test power reduction technique consequently. The approach does not specify any ordering inside the chains and fits seamlessly to any standard tool for scan chain integration. The application of known test power reduction techniques to the optimized scan chain configurations shows significant improvements for large industrial circuits.