Test Scheduling and Control for VLSI Built-in Self-Test
IEEE Transactions on Computers
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems
ATS '99 Proceedings of the 8th Asian Test Symposium
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
BIST hardware synthesis for RTL data paths based on test compatibility classes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testability Trade-Offs for BIST Data Paths
Journal of Electronic Testing: Theory and Applications
Scan test planning for power reduction
Proceedings of the 44th annual Design Automation Conference
Scan chain clustering for test power reduction
Proceedings of the 45th annual Design Automation Conference
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BIST increases circuit activity and hence power in data path circuits. The voltage drop that occurs during testing causes some good circuits to fail the testing process, leading to unnecessary manufacturing yield loss. Addressing this problem, the authors show how test synthesis and test scheduling affect power dissipation and present new power-conscious algorithms.