Built-in self-test support in the IBM engineering design system
IBM Journal of Research and Development
IEEE Transactions on Computers - Special issue on fault-tolerant computing
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Low Power BIST by Filtering Non-Detecting Vectors
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Test and Reliability: Partners in IC Manufacturing, Part 1
IEEE Design & Test
Test and Reliability: Partners in IC Manufacturing, Part 2
IEEE Design & Test
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Reducing Power Dissipation during Test Using Scan Chain Disable
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Power-Conscious Test Synthesis and Scheduling
IEEE Design & Test
Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Scalable selector architecture for x-tolerant deterministic BIST
Proceedings of the 41st annual Design Automation Conference
Test response compactor with programmable selector
Proceedings of the 43rd annual Design Automation Conference
Design and analysis of compact dictionaries for diagnosis in scan-BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Creating small fault dictionaries [logic circuit fault diagnosis]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan chain clustering for test power reduction
Proceedings of the 45th annual Design Automation Conference
Power management using test-pattern ordering for wafer-level test during burn-in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can be used for reducing the power consumption during test. Here, we present an efficient algorithm for the automated generation of a test plan that keeps fault coverage as well as test time, while significantly reducing the amount of wasted energy. A fault isolation table, which is usually used for diagnosis and debug, is employed to accurately determine scan chains that can be disabled. The algorithm was successfully applied to large industrial circuits and identifies a very large amount of excess pattern shift activity.