Logic BIST for Large Industrial Designs: Real Issues and Case Studies

Authors:
Graham Hetherington;Tony Fryars;Nagesh Tamarapalli;Mark Kassab;Abu Hassan;Janusz Rajski
Affiliations:
-;-;-;-;-;-
Venue:
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Year:
1999

Citing 9
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Abstract

This paper discusses practical issues involved in applyinglogic built-in self-test (BIST) to four large industrialdesigns. These multi-clock designs, ranging in size from200K to 800K gates, pose significant challenges to logicBIST methodology, flow, and tools. The paper presents theprocess of generating a BIST-compliant core along with thelogic BIST controller for at-speed testing. Comparativedata on fault grades and area overhead between automatictest pattern generation (ATPG) and logic BIST arereported. The experimental results demonstrate that withautomation of the proposed solutions, logic BIST canachieve test quality approaching that of ATPG with minimalarea overhead and few changes to the design flow.