IEEE Spectrum
On Multiple Path Propagating Tests for Path Delay Faults
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Diagnosis of parametric path delay faults
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Tutorial: Delay Fault Models and Coverage
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
An algebraic method for delay fault testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
An optimized BIST test pattern generator for delay testing
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Delay fault coverage, test set size, and performance trade-offs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High Defect Coverage with Low-Power Test Sequences in a BIST Environment
IEEE Design & Test
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient architecture for accumulator-based test generation of SIC pairs
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An effective two-pattern test generator for Arithmetic BIST
Computers and Electrical Engineering
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The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when high robust delay fault coverage is targeted. In this paper, we show that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non-robust tests are under consideration. Experimental results given in this paper are based on a software generation of RSIC test sequences that can be easily generated in this case. For a built-in self-test (BIST) purpose, hardware generated RSIC sequences have to be used. This kind of generation will be shortly discussed at the end of the paper.