Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences
ETW '00 Proceedings of the IEEE European Test Workshop
On Hardware Generation of Random Single Input Change Test Sequences
ETW '01 Proceedings of the IEEE European Test Workshop (ETW'01)
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A new technique, random single-input change (RSIC) test generation, generates low-power test patterns that provide a high level of defect coverage during low-power BIST of digitalcircuits. The authors propose a parallel BIST implementation of the RSIC generator and analyze its area-overhead impact.