Introduction to IDDQ testing
Testing in nanometer technologies
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Test Routines Based on Symbolic Logical Statements
Journal of the ACM (JACM)
Finding Defects with Fault Models
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test generation for resistive opens in CMOS
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits
Journal of Electronic Testing: Theory and Applications
CMOS Differential and Absolute Thermal Sensors
Journal of Electronic Testing: Theory and Applications
The Mutating Metric for Benchmarking Test
IEEE Design & Test
Online Testing Approach for Very Deep-Submicron ICs
IEEE Design & Test
High Defect Coverage with Low-Power Test Sequences in a BIST Environment
IEEE Design & Test
On theoretical and practical considerations of path selection for delay fault testing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 40th annual Design Automation Conference
Effects of Multi-cycle Sensitization on Delay Tests
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Precise Test Generation for Resistive Bridging Faults of CMOS Combinational Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improving Fault Coverage in System Tests
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A new test pattern generator for high defect coverage in a BIST environment
Proceedings of the 14th ACM Great Lakes symposium on VLSI
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A new classification of path-delay fault testability in terms of stuck-at faults
Journal of Computer Science and Technology
Experience in critical path selection for deep sub-micron delay test and timing validation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Graph partition based path selection for testing of small delay defects
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
| Hi-index | 4.10 |
The introduction of nanometer technologies into the imperfect manufacturing process of ICs presents new challenges for identifying defects that creep into some fabricated chips. Defects are unpredictable in both location and effect, and the processes that cause them include a wide range of variables. These defects can take a variety of forms, from localized spot defects-typically extra or missing material caused by particles-to defects affecting much larger areas, such as reduced capacitance caused by inadequate implantation. To simplify the identification of defective circuits, this infinite defect space is approximated by a finite set of faults. Faults are deterministic, discrete changes in circuit behavior. They are often considered localized within a circuit (for example, when a particular gate is broken) and can also be thought of as transformations that change the Boolean function implemented by a circuit. Research into fault models has generated new methods for extending them from the gate level to the presynthesized register-transfer-level (RTL) and behavioral code. Chip designers can use simple models-such as stuck-at faults-to find a wide variety of defects. Nanometer technologies will require innovative delay fault models and techniques to extend the life of test methods like IDDQ.