Hierarchical Delay Test Generation
Journal of Electronic Testing: Theory and Applications
Test challenges for deep sub-micron technologies
Proceedings of the 37th Annual Design Automation Conference
ClariNet: a noise analysis tool for deep submicron design
Proceedings of the 37th Annual Design Automation Conference
Performance sensitivity analysis using statistical method and its applications to delay
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
On theoretical and practical considerations of path selection for delay fault testing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
T4: New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Path delay fault diagnosis and coverage-a metric and an estimation technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
Proceedings of the 41st annual Design Automation Conference
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits
Journal of Electronic Testing: Theory and Applications
Path selection for monitoring unexpected systematic timing effects
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Hi-index | 0.00 |
Critical path selection is an indispensable step for AC delay test and timing validation. Traditionally, this step relies on the construction of a set of worse-case paths based upon discrete timing models. However, the assumption of discrete timing models can be invalidated by timing defects and process variation in the deep sub-micron domain, which are often continuous in nature. As a result, critical paths defined in a traditional timing analysis approach may not be truly critical in reality. In this paper, we propose using a statistical delay evaluation framework for estimating the quality of a path set. Based upon the new framework, we demonstrate how the traditional definition of a critical path set may deviate from the true critical path set in the deep sub-micron domain. To remedy the problem, we discuss improvements to the existing path selection strategies by including new objectives. We then compare statistical approaches with traditional approaches based upon experimental analysis of both defect-free and defect-injected cases.