Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits

Authors:
Bipul C. Paul;Kaushik Roy
Affiliations:
Toshiba America Research Inc., San Jose, USA 95131;School of Electrical and Computer Engineering, Purdue University, West Lafayette, USA 47907-1285
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2006

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Abstract

A technique for implementing totally symmetric Boolean functions using hierarchical modules is presented. First, a simple cellular module is designed for synthesizing unate symmetric functions. The structure is universal, admits a recursive design, and ...