Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
A process-tolerant cache architecture for improved yield in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Statistical design and optimization of SRAM cell for yield enhancement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Variability in sub-100nm SRAM designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Magnetic tunnelling junction based FPGA
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Leakage current starved domino logic
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits
Journal of Electronic Testing: Theory and Applications
Statistical analysis of SRAM cell stability
Proceedings of the 43rd annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Microprocessors in the era of terascale integration
Proceedings of the conference on Design, automation and test in Europe
Device-aware yield-centric dual-Vt design under parameter variations in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MATH'05 Proceedings of the 8th WSEAS International Conference on Applied Mathematics
The impact of random device variation on SRAM cell stability in sub-90-nm CMOS technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits
Microelectronics Journal
Error-resilient motion estimation architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays
Microelectronics Journal
Characterization of a novel nine-transistor SRAM cell
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SRAM dynamic stability estimation using MPFP and its applications
Microelectronics Journal
Statistical design of the 6T SRAM bit cell
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Source/drain optimization of underlapped lightly doped nanoscale double-gate MOSFETs
Microelectronic Engineering
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Testing random defect and process variation induced comparison faults of TCAMs with asymmetric cells
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Stochastic networked computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Data memory subsystem resilient to process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate estimation of SRAM dynamic stability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DEFCAM: A design and evaluation framework for defect-tolerant cache memories
ACM Transactions on Architecture and Code Optimization (TACO)
Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes
Journal of Electronic Testing: Theory and Applications
Hardware/software approaches for reducing the process variation impact on instruction fetches
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Intrinsic fluctuations in threshold voltage, subthreshold swing, saturation drain current and subthreshold leakage of ultrasmall-geometry MOSFETs due to random placement of dopant atoms in the channel are examined using novel physical models and a Monte Carlo simulator. These fluctuations are shown to pose severe barriers to the scaling of supply voltage and channel length and thus, to the minimization of power dissipation and switching delay in multibillion transistor chips of the future. In particular, using the device technology and the level of integration projections of the National Technology Roadmap for Semiconductors for the next 15 years, standard and maximum deviations of threshold voltage, drive current, subthreshold swing and subthreshold leakage are shown to escalate to 40 and 600 mV, 10 and 100%, 2 and 20 mV/dec, and 10 and 10/sup 8/%, respectively, in the 0.07 /spl mu/m, 0.9 V complementary metal-oxide-semiconductor (CMOS) technology generation with 1.3-64 billion transistors on a chip in 2010. While these deviations can be reduced to some degree by selecting optimal values of channel width, the associated penalties in dynamic and static power, and in packing density demand improved MOSFET structures aimed at minimizing parameter deviations.