Intrinsic MOSFET parameter fluctuations due to random dopant placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Analysis of dual-Vt SRAM cells with full-swing single-ended bit line sensing for on-chip cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Life is CMOS: why chase the life after?
Proceedings of the 39th annual Design Automation Conference
Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
Implementation of low-voltage static RAM with enhanced data stability and circuit speed
Microelectronics Journal
Design and analysis of two low-power SRAM cell structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design hardening of nanometer SRAMs through transistor width modulation and multi-Vt combination
IEEE Transactions on Circuits and Systems II: Express Briefs
Single ended 6T SRAM with isolated read-port for low-power embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
A 7T SRAM bit-cell for low-power embedded memories
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM
Integration, the VLSI Journal
A read-decoupled gated-ground SRAM architecture for low-power embedded memories
Integration, the VLSI Journal
Single-ended, robust 8T SRAM cell for low-voltage operation
Microelectronics Journal
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Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. A new nine-transistor (9T) SRAM cell is proposed in this paper for simultaneously reducing leakage power and enhancing data stability. The proposed 9T SRAM cell completely isolates the data from the bit lines during a read operation. The read static-noise-margin of the proposed circuit is thereby enhanced by 2 × as compared to a conventional six-transistor (6T) SRAM cell. The idle 9T SRAM cells are placed into a super cutoff sleep mode, thereby reducing the leakage power consumption by 22.9% as compared to the standard 6T SRAM cells in a 65-nm CMOS technology. The leakage power reduction and read stability enhancement provided with the new circuit technique are also verified under process parameter variations.