SRAM Leakage Suppression by Minimizing Standby Supply Voltage
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
A Feasibility Study of Subthreshold SRAM Across Technology Generations
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A new single-ended SRAM cell with write-assist
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Implementation of low-voltage static RAM with enhanced data stability and circuit speed
Microelectronics Journal
Characterization of a novel nine-transistor SRAM cell
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SRAM write-ability improvement with transient negative bit-line voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Single-ended subthreshold SRAM with asymmetrical write/read-assist
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Recently, an SRAM has been in the development stage, with its objective to withstand the ever-increasing process variations as well as to support ultra-low power applications, even at subthreshold supply voltages. In this paper, a new 8T SRAM cell, which employs a single bitline scheme to perform the write and read operations, is proposed. This scheme enhances the write ability and read stability by cutting off the feedback loop of the inverter pair, thereby eliminating the read and write constraints on the transistor dimensions. Additionally, it efficiently trims down the write power and standby power consumption. The experimental results show that the proposed 8T cell achieves 4.66x write ability, 2.33x read noise margin, 28.0% write power reduction, and 3.3x lower standby power dissipation when compared with a 6T bit-cell at 0.5V through a Monte Carlo simulation (10,000 times) using the TSMC 65-nm process. Moreover, it also achieves higher process variation tolerance at an ultralow operating voltage.