Single-ended subthreshold SRAM with asymmetrical write/read-assist

Authors:
Ming-Hsien Tu;Jihi-Yu Lin;Ming-Chien Tsai;Shyh-Jye Jou;Ching-Te Chuang
Affiliations:
Electronics Engineering Department and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.;Electronics Engineering Department and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.;Electronics Engineering Department and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.;Electronics Engineering Department and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.;Electronics Engineering Department and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
Year:
2010

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Abstract

In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V VDD, an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 µW.