IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
CMOS memory circuits
Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters in Configurable Memory Designs
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SRAM Cell Current in Low Leakage Design
MTDT '06 Proceedings of the 2006 IEEE International Workshop on Memory Technology, Design, and Testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Circuits and Systems II: Express Briefs
Self-timed SRAM for energy harvesting systems
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Single-ended subthreshold SRAM with asymmetrical write/read-assist
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
Improving the robustness of self-timed SRAM to variable Vdds
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
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Voltage-dependent timing skews in precharge and sensing activities cause functional failure and reduce the speed of asynchronous static random-access memory (SRAM). Data-dependent bitline-leakage current further increases the timing skews and reduces the yield of asynchronous SRAM. A dual-mode self-timed (DMST) technique is developed for asynchronous SRAM to eliminate the timing-skew-induced failures and speed overhead across various process, voltage, and temperature conditions. The DMST technique employs a single replica column and new dummy cells to track both precharge and sensing activities in asynchronous SRAM, with bitline leakage considered. The DMST-technique simulation uses both 65-nm and 0.35-µm technologies. Several 0.35-µm DMST SRAM macros were fabricated in a test chip and embedded in a mass-produced system-on-a-chip suitable for various battery/supply-voltage configurations. Measurements demonstrated that the DMST technique can be operated continuously over a wide range of supply voltages, from 39.4% to 151.5% (or 212.1%, given device durability) of the nominal supply voltage (3.3 V). The fabricated macros also confirmed that the DMST technique is scalable for various bitline lengths and offers the same area overhead as conventional sense-tracking-only replica-column schemes.