A 0.45-V 300-MHz 10T flowthrough SRAM with expanded WRITE/READ stability and speed-area-wise array for sub-0.5-V chips

Authors:
Meng-Fan Chang;Yung-Chi Chen;Chien-Fu Chen
Affiliations:
Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan;Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan;Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2010

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Abstract

Capable of only solving the READ-stability issue, many 8T-10T static RAM (SRAM) cells require extra WRITE-assist circuits to achieve low supply voltage operation. This brief proposes a novel 10T SRAM cell and a hybrid-divided-block array to enhance the READ-and-WRITE stability while achieving a higher operating speed with a smaller area overhead for sub-0.5 V applications. A 16-Kb 128-row 10T flowthrough SRAM macro is fabricated using a 90-nm bulk-CMOS process. The 10T cell area is only 1.7 times the size of a 6T cell. The measured VDDmin for the 10T 16-Kb macro is 240 mV. The proposed 16-Kb macro can achieve 300-MHz random access operation at 0.45 V for a 0.5 V system platform.