Statistical design of the 6T SRAM bit cell

Authors:
Vasudha Gupta;Mohab Anis
Affiliations:
Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada;Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2010

Citing 15
Cited 3

Digital integrated circuits: a design perspective

Digital integrated circuits: a design perspective
Intrinsic MOSFET parameter fluctuations due to random dopant placement

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Fundamentals of modern VLSI devices

Fundamentals of modern VLSI devices
Subwavelength lithography and its potential impact on design and EDA

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Statistical optimization of leakage power considering process variations using dual-Vth and sizing

Proceedings of the 41st annual Design Automation Conference
Ultralow-power SRAM technology

IBM Journal of Research and Development
Gate Leakage and Its Reduction in Deep Submicron SRAM

VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Variability in sub-100nm SRAM designs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Backend CAD flows for "restrictive design rules"

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Variability-aware device optimization under ION and leakage current constraints

Proceedings of the 2006 international symposium on Low power electronics and design
High-performance CMOS variability in the 65-nm regime and beyond

IBM Journal of Research and Development - Advanced silicon technology
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A 0.45-V 300-MHz 10T flowthrough SRAM with expanded WRITE/READ stability and speed-area-wise array for sub-0.5-V chips

IEEE Transactions on Circuits and Systems II: Express Briefs
A statistical yield optimization framework for interconnect in double patterning lithography

Microelectronics Journal
Statistical SRAM read access yield improvement using negative capacitance circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, a method for the statistical design of the static-random-access-memory bit cell is proposed to ensure a high memory yield while meeting design specifications for performance, stability, area, and leakage. The method generates the nominal design parameters, i.e., the widths and lengths of the bit-cell transistors, which provide maximum immunity to the variations in a transistor's dimensions and intrinsic threshold-voltage fluctuations. Moreover, the need to deviate from the conventional bitcell sizing strategy to obtain a high-yield low-leakage design in the nanometer regime is demonstrated.