Statistical optimization of leakage power considering process variations using dual-Vth and sizing

Authors:
Ashish Srivastava;Dennis Sylvester;David Blaauw
Affiliations:
University of Michigan, Ann Arbor, MI;University of Michigan, Ann Arbor, MI;University of Michigan, Ann Arbor, MI
Venue:
Proceedings of the 41st annual Design Automation Conference
Year:
2004

Citing 15
Cited 39

The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Static power optimization of deep submicron CMOS circuits for dual VT technology

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Uncertainty-aware circuit optimization

Proceedings of the 39th annual Design Automation Conference
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

Proceedings of the 39th annual Design Automation Conference
A general probabilistic framework for worst case timing analysis

Proceedings of the 39th annual Design Automation Conference
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS

Proceedings of the 2002 international symposium on Low power electronics and design
Standby power optimization via transistor sizing and dual threshold voltage assignment

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Parameter variations and impact on circuits and microarchitecture

Proceedings of the 40th annual Design Automation Conference
Computation and Refinement of Statistical Bounds on Circuit Delay

Proceedings of the 40th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits

Proceedings of the 40th annual Design Automation Conference
Statistical estimation of leakage current considering inter- and intra-die process variation

Proceedings of the 2003 international symposium on Low power electronics and design
Optimal body bias selection for leakage improvement and process compensation over different technology generations

Proceedings of the 2003 international symposium on Low power electronics and design
Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

Optimization objectives and models of variation for statistical gate sizing

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
An efficient algorithm for statistical minimization of total power under timing yield constraints

Proceedings of the 42nd annual Design Automation Conference
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance

Proceedings of the 42nd annual Design Automation Conference
Leakage minimization of nano-scale circuits in the presence of systematic and random variations

Proceedings of the 42nd annual Design Automation Conference
Probabilistic dual-Vth leakage optimization under variability

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
General transistor-level methodology on VLSI low-power design

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Statistical technology mapping for parametric yield

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS)

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing using incremental parameterized statistical timing analysis

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Yield prediction for architecture exploration in nanometer technology nodes:: a model and case study for memory organizations

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Comparative analysis of conventional and statistical design techniques

Proceedings of the 44th annual Design Automation Conference
System-on-chip power management considering leakage power variations
Minimizing leakage: what if every gate could have its individual threshold voltage?

AIAP'07 Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: artificial intelligence and applications
Device-aware yield-centric dual-Vt design under parameter variations in nanoscale technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing variation-aware high-level synthesis

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Soft-edge flip-flops for improved timing yield: design and optimization

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Variation-aware gate sizing and clustering for post-silicon optimized circuits

Proceedings of the 13th international symposium on Low power electronics and design
Scheduling task dependence graphs with variable task execution times onto heterogeneous multiprocessors

EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
Timing variation-aware task scheduling and binding for MPSoC

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On the futility of statistical power optimization

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A fuzzy optimization approach for variation aware power minimization during gate sizing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware multimetric optimization during gate sizing

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Statistical design of the 6T SRAM bit cell

IEEE Transactions on Circuits and Systems Part I: Regular Papers
Post-manufacture tuning for nano-CMOS yield recovery using reconfigurable logic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MODEST: a model for energy estimation under spatio-temporal variability

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Inversed temperature dependence aware clock skew scheduling for sequential circuits

Proceedings of the Conference on Design, Automation and Test in Europe
Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Design time body bias selection for parametric yield improvement

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Evaluating statistical power optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Biologically-Inspired optimization of circuit performance and leakage: a comparative study

ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Low power FPGA design using post-silicon device aging (abstract only)

Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Static statistical MPSoC power optimization by variation-aware task and communication scheduling

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Increasing levels of process variability in sub-100nm CMOS design has become a critical concern for performance and power constraint designs. In this paper, we propose a new statistically aware Dual-Vt and sizing optimization that considers both the variability in performance and leakage of a design. While extensive work has been performed in the past on statistical analysis methods, circuit optimization is still largely performed using deterministic methods. We show in this paper that deterministic optimization quickly looses effectiveness for stringent performance and leakage constraints in designs with significant variability. We then propose a statistically aware dual-Vt and sizing algorithm where both delay constraints and sensitivity computations are performed in a statistical manner. We demonstrate that using this statistically aware optimization, leakage power can be reduced by 15-35% compared to traditional deterministic analysis. The improvements increase for strict delay constraints making statistical optimization especially important for high performance designs.