Mixed-Vth (MVT) CMOS circuit design methodology for low power applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Switch-level delay models for digital MOS VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
CMOS gate delay models for general RLC loading
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Proceedings of the 2003 international symposium on Low power electronics and design
Selective gate-length biasing for cost-effective runtime leakage control
Proceedings of the 41st annual Design Automation Conference
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Proceedings of the 42nd annual Design Automation Conference
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Effective analytical delay model for transistor sizing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
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In this work, we modify the Alpha-Power Law to accurately simulate BSIM3-70nm gate delay on transistor level. Combined with efficient power analysis methods, we develop one transistor-level simulator to efficient estimate performance and power for CMOS gates consisting of heterogeneous transistors. Furthermore, we propose a novel transistor-level optimization engine consisting of two-step algorithms. The former gate-space algorithm uses the clustering strategy to cut down algorithm complexity. The latter transistor-space algorithm employs fine granularity to pursue reducing more power consumption. Experiments show the following advantages: 1. Our transistor-level simulator takes average 1.0ms (on an ordinary PM1.4G-256M laptop computer) to analyze one gate and can accurately estimate circuit delay with only 2-7% worst-case error. 2. Our methodology is so general that it can analyze and optimize heterogeneous circuit in which each transistor may have its own different VT0, channel width and length. 3. In the transistor-level width+VT0+length-sized optimization, our engine takes feasible running time (856.4s for C7552) to cut down 22.58%(average) and 43.02%(maximum) leakage power caused by gate-level optimum solution nearly without penalty of active power.