Dynamic CMOS load balancing and path oriented in time optimization algorithms to minimize delay uncertainties from process variations

Authors:
Kumar Yelamarthi;Chien-In Henry Chen
Affiliations:
School of Engineering and Technology, Central Michigan University, Mt Pleasant, MI;Department of Electrical Engineering, Wright State University, Dayton, OH
Venue:
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
Year:
2010

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Abstract

The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixed-static-dynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and International Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an average improvement in delay by 38% and delay uncertainty from process variations by 35% in comparison with a state-of-the-art commercial optimization tool.