First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 42nd annual Design Automation Conference
Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd annual Design Automation Conference
Process and environmental variation impacts on ASIC timing
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
The impact of device parameter variations on the frequency and performance of VLSI chips
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing analysis in presence of supply voltage and temperature variations
Proceedings of the 2006 international symposium on Physical design
Statistical timing analysis with two-sided constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty
Proceedings of the 43rd annual Design Automation Conference
An IC manufacturing yield model considering intra-die variations
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Worst-case delay analysis considering the variability of transistors and interconnects
Proceedings of the 2007 international symposium on Physical design
Minimal skew clock embedding considering time variant temperature gradient
Proceedings of the 2007 international symposium on Physical design
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Statistical Timing Analysis Considering Spatial Correlations
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
Characterizing process variation in nanometer CMOS
Proceedings of the 44th annual Design Automation Conference
A framework for accounting for process model uncertainty in statistical static timing analysis
Proceedings of the 44th annual Design Automation Conference
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
| Hi-index | 0.00 |
Design margining is used to account for design uncertainties in the measurement of performance, and thereby ensures that actual manufactured parts will operate in within predicted bounds. As process and environmental variations become increasingly severe and complex in nanometer process technology, design margining overheads have increased correspondingly. This paper describes the types of process and environmental variations, their impact on performance, and the traditional design margining process used to account for these uncertainties. We consider statistical timing (SSTA) in the context of its ability to reduce timing margins through more accurate modeling of variations, and quantify potential benefits of SSTA for setup and hold time margin reduction. Combining SSTA with complementary techniques for systematic variation-aware and voltage-variation-aware timing provides meaningful design margin reduction. We introduce the concept of activity based operating condition as a supporting construct for variation-aware STA flows