Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
The impact of device parameter variations on the frequency and performance of VLSI chips
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 42nd annual Design Automation Conference
Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd annual Design Automation Conference
On the need for statistical timing analysis
Proceedings of the 42nd annual Design Automation Conference
The impact of device parameter variations on the frequency and performance of VLSI chips
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Application of fast SOCP based statistical sizing in the microprocessor design flow
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Analyzing timing uncertainty in mesh-based clock architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Statistical circuit optimization considering device andinterconnect process variations
Proceedings of the 2007 international workshop on System level interconnect prediction
Analysis and modeling of CD variation for statistical static timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Variations, margins, and statistics
Proceedings of the 2008 international symposium on Physical design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
Process variation aware thread mapping for chip multiprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The distance-correlated (continuous) within-die (WID) process variations of transistor parameters appears to be approximately scaling with process generations. Furthermore, shrinking clock cycles and the scaling of functional block dimensions in complex chips (e.g. CPUs), cause a shortening of interconnect distances. These effects mitigate correlated variations' impact on delay changes across a die. Temperature has a small effect, and supply distribution can be well-understood and designed. Furthermore, uncorrelated (random) variations (e.g. RDF, & LER) currently have a small impact on speed-setting paths, and even multiplying their effect (as processes shrink), would not make them very significant. Coupled with methods for estimating the shift in the maximum operating frequency (F/sub max/) of a die (due to variations), it is shown that variations will continue to have a small effect on product speeds through the mid-term future.