Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the 42nd annual Design Automation Conference
The impact of device parameter variations on the frequency and performance of VLSI chips
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Post-silicon timing characterization by compressed sensing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Stochastic thermal simulation considering spatial correlated within-die process variations
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Timing analysis with compact variation-aware standard cell models
Integration, the VLSI Journal
Accurate temperature estimation using noisy thermal sensors
Proceedings of the 46th Annual Design Automation Conference
FPGA design for timing yield under process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Via wearout detection with on-chip monitors
Microelectronics Journal
Process-variation resilient and voltage scalable DCT architecture for robust low-power computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust spatial correlation extraction with limited sample via L1-norm penalty
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Matched public PUF: ultra low energy security platform
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Integrated circuit digital rights management techniques using physical level characterization
Proceedings of the 11th annual ACM workshop on Digital rights management
Robust passive hardware metering
Proceedings of the International Conference on Computer-Aided Design
Wireless security techniques for coordinated manufacturing and on-line hardware trojan detection
Proceedings of the fifth ACM conference on Security and Privacy in Wireless and Mobile Networks
Provably complete hardware trojan detection using test point insertion
Proceedings of the International Conference on Computer-Aided Design
Using standardized quantization for multi-party PPUF matching: foundations and applications
Proceedings of the International Conference on Computer-Aided Design
Low power FPGA design using post-silicon device aging (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Energy attacks and defense techniques for wireless systems
Proceedings of the sixth ACM conference on Security and privacy in wireless and mobile networks
Scalable hardware trojan diagnosis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient method for analyzing on-chip thermal reliability considering process variations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much research has focused on the modeling of spatial correlation in SSTA. However, the vast majority of these works used artificially generated process data to test the proposed models. Hence, it is difficult to determine the actual effectiveness of these methods, the conditions under which they are necessary, and whether they lead to a significant increase in accuracy that warrants their increased runtime and complexity. In this paper, we study 5 different correlation models and their associated SSTA methods using 35420 critical dimension (CD) measurements that were extracted from 23 reticles on 5 wafers in a 130nm CMOS process. Based on the measured CD data, we analyze the correlation as a function of distance and generate 5 distinct correlation models, ranging from simple models which incorporate one or two variation components to more complex models that utilize principle component analysis and Quad-trees. We then study the accuracy of the different models and compare their SSTA results with the result of running STA directly on the extracted data. We also examine the trade-off between model accuracy and run time, as well as the impact of die size on model accuracy. We show that, especially for small dies (