Via wearout detection with on-chip monitors

Authors:
Fahad Ahmed;Linda Milor
Affiliations:
Georgia Institute of Technology, School of Electrical and Computer Engineering, Atlanta, GA 30332, USA;Georgia Institute of Technology, School of Electrical and Computer Engineering, Atlanta, GA 30332, USA
Venue:
Microelectronics Journal
Year:
2010

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Abstract

This project aims to detect the onset of chip failure due to via voiding through monitoring the delays of paths in a chip. The proposed method relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65nm technology. The delay increase, as a function of the failure distribution parameters, the path length, gate type, and process variation, has been investigated. An on-chip, ring oscillator-based wearout monitoring circuit is presented. The proposed scheme monitors the delay through a data path using a delay detection circuit (DDC).