Advances in Computation of the Maximum of a Set of Random Variables
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Variation-aware routing for FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analysis and modeling of CD variation for statistical static timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An accurate sparse matrix based framework for statistical static timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Statistical model order reduction for interconnect circuits considering spatial correlations
Proceedings of the conference on Design, automation and test in Europe
Confidence scalable post-silicon statistical delay prediction under process variations
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 44th annual Design Automation Conference
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
Proceedings of the 2008 international symposium on Physical design
Statistical gate delay model for multiple input switching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Statistical timing analysis of flip-flops considering codependent setup and hold times
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A lithography-friendly structured ASIC design approach
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Utilizing redundancy for timing critical interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A framework for block-based timing sensitivity analysis
Proceedings of the 45th annual Design Automation Conference
An expected-utility based approach to variation aware VLSI optimization under scarce information
Proceedings of the 13th international symposium on Low power electronics and design
Transistor-specific delay modeling for SSTA
Proceedings of the conference on Design, automation and test in Europe
On efficient Monte Carlo-based statistical static timing analysis of digital circuits
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Process variability-aware transient fault modeling and analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Stochastic thermal simulation considering spatial correlated within-die process variations
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Accelerating statistical static timing analysis using graphics processing units
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Synthesizing a representative critical path for post-silicon delay prediction
Proceedings of the 2009 international symposium on Physical design
Timing analysis with compact variation-aware standard cell models
Integration, the VLSI Journal
Variation-aware multimetric optimization during gate sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Statistical static timing analysis considering leakage variability in power gated designs
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
A Gaussian mixture model for statistical timing analysis
Proceedings of the 46th Annual Design Automation Conference
A parametric approach for handling local variation effects in timing analysis
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and accurate statistical criticality computation under process variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast statistical analysis of process variation effects using accurate PLL behavioral models
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Adjustment-based modeling for timing analysis under variability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A framework for scalable postsilicon statistical delay prediction under process variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2009 International Conference on Computer-Aided Design
Robust simulation methodology for surface-roughness loss in interconnect and package modelings
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Process variation-aware performance analysis of asynchronous circuits
Microelectronics Journal
FPGA design for timing yield under process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 47th Design Automation Conference
Full-chip leakage analysis for 65nm CMOS technology and beyond
Integration, the VLSI Journal
Practical Monte-Carlo based timing yield estimation of digital circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Advanced variance reduction and sampling techniques for efficient statistical timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical leakage power optimization of asynchronous circuits considering process variations
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Statistical timing yield optimization by gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Handling intra-die variations in PSTA
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Proceedings of the 48th Design Automation Conference
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Structured analog circuit design and MOS transistor decomposition for high accuracy applications
Proceedings of the International Conference on Computer-Aided Design
Effect of process variations in 3D global clock distribution networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
An accurate sparse-matrix based framework for statistical static timing analysis
Integration, the VLSI Journal
Computation of joint timing yield of sequential networks considering process variations
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
A statistical model of logic gates for Monte Carlo simulation including on-chip variations
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Timing yield analysis considering process-induced temperature and supply voltage variations
Microelectronics Journal
On the computation of criticality in statistical timing analysis
Proceedings of the International Conference on Computer-Aided Design
Power yield analysis under process and temperature variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integration, the VLSI Journal
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Process variations are of increasing concern in today's technologies, and they can significantly affect circuit performance. An efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay considering both inter-die and intra-die variations, while accounting for the effects of spatial correlations of intra-die parameter variations, is presented. The procedure uses a first-order Taylor series expansion to approximate the gate and interconnect delays. Next, principal component analysis (PCA) techniques are employed to transform the set of correlated parameters into an uncorrelated set. The statistical timing computation is then easily performed with a program evaluation and review technique (PERT)-like circuit graph traversal. The run time of this algorithm is linear in the number of gates and interconnects, as well as the number of varying parameters and grid partitions that are used to model spatial correlations. The accuracy of the method is verified with Monte Carlo (MC) simulation. On average, for the 100 nm technology, the errors of mean and standard deviation (SD) values computed by the proposed method are 1.06% and -4.34%, respectively, and the errors of predicting the 99% and 1% confidence point are -2.46% and -0.99%, respectively. A testcase with about 17 800 gates was solved in about 500 s, with high accuracy as compared to an MC simulation that required more than 15 h.