Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
The effect of process variation on device temperature in FinFET circuits
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
A novel table-based approach for design of FinFET circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the Conference on Design, Automation and Test in Europe
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design space exploration of FinFET cache
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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We present CACTI-FinFET, an integrated framework for simulation of power, delay, temperature, as well as process variations of FinFET-based caches. We have developed a FinFET design library and process variation models to characterize the delay and leakage spreads of such caches. We present results for various FinFET design styles and show that mixing different design styles may be a promising strategy for optimizing cache delay and leakage.