Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Efficient Monte Carlo based incremental statistical timing analysis
Proceedings of the 45th annual Design Automation Conference
Practical, fast Monte Carlo statistical static timing analysis: why and how
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Proceedings of the 46th Annual Design Automation Conference
SRAM parametric failure analysis
Proceedings of the 46th Annual Design Automation Conference
Pragmatic design of gated-diode FinFET DRAMs
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Proceedings of the 47th Design Automation Conference
Gated-diode FinFET DRAMs: Device and circuit design-considerations
ACM Journal on Emerging Technologies in Computing Systems (JETC)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 48th Design Automation Conference
Maximum-information storage system: concept, implementation and application
Proceedings of the International Conference on Computer-Aided Design
A lower bound computation method for evaluation of statistical design techniques
Proceedings of the International Conference on Computer-Aided Design
Formal verification of analog circuit parameters across variation utilizing SAT
Proceedings of the Conference on Design, Automation and Test in Europe
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Problems in computational finance share many of the characteristics that challenge us in statistical circuit analysis: high dimensionality, profound nonlinearity, stringent accuracy requirements, and expensive sample simulation. We offer a detailed experimental study of how one celebrated technique from this domain -- Quasi-Monte Carlo (QMC) analysis -- can be used for fast statistical circuit analysis. In contrast with traditional pseudo-random Monte Carlo sampling, QMC substitutes a (shorter) sequence of deterministically chosen sample points. Across a set of digital and analog circuits, in 90nm and 45nm technologies, varying in size from 30 to 400 devices, we obtain speedups in parametric yield estimation from 2X to 50X.