Surface simplification using quadric error metrics
Proceedings of the 24th annual conference on Computer graphics and interactive techniques
A formal approach to verification of linear analog circuits wth parameter tolerances
Proceedings of the conference on Design, automation and test in Europe
Model checking algorithms for analog verification
Proceedings of the 39th annual Design Automation Conference
Superfaces: Polygonal Mesh Simplification with Bounded Error
IEEE Computer Graphics and Applications
The complexity of theorem-proving procedures
STOC '71 Proceedings of the third annual ACM symposium on Theory of computing
Towards formal verification of analog designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Verification of analog/mixed-signal circuits using labeled hybrid petri nets
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Fast statistical circuit analysis with finite-point based transistor model
Proceedings of the conference on Design, automation and test in Europe
Review: Formal verification of analog and mixed signal designs: A survey
Microelectronics Journal
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
First steps towards SAT-based formal analog verification
Proceedings of the 2009 International Conference on Computer-Aided Design
Formal Verification of C-element Circuits
ASYNC '11 Proceedings of the 2011 17th IEEE International Symposium on Asynchronous Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of digital circuits through symbolic reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Circuit analysis and optimization driven by worst-case distances
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A fast technique for proving steady-state analog circuit operation constraints is described. Based on SAT, the technique is applicable to practical circuit design and modeling scenarios as it does not require algebraic device models. Despite the complexity of representing accurate transistor I/V characteristics, run-time and problem scaling behavior is excellent.