A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
SOI Transistor Model for Fast Transient Simulation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 42nd annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MOSFET modeling for 45nm and beyond
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A robust finite-point based gate model considering process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An efficient method for statistical circuit simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
The Predictive Technology Model in the Late Silicon Era and Beyond
Foundations and Trends in Electronic Design Automation
RDE-based transistor-level gate simulation for statistical static timing analysis
Proceedings of the 47th Design Automation Conference
Formal verification of analog circuit parameters across variation utilizing SAT
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
A new approach of transistor modeling is developed for fast statistical circuit simulation in the presence of variations. For both I-V and C-V characteristics of a transistor, finite data points are identified by their physical meaning; the impact of process and design variations is embedded into these points as closed-form expressions. Then, the entire I-V and C-V are extrapolated using polynomial formulas. This novel approach significantly enhances the simulation speed with sufficient accuracy. The model is implemented in Verilog-A at 65nm node. Compared to simulations with the BSIM model, the computation time can be reduced by 7x in transient analysis and 9x in Monte-Carlo simulations.