Closing the gap between ASIC and custom: an ASIC perspective
Proceedings of the 37th Annual Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
A probabilistic approach to clock cycle prediction
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
From blind certainty to informed uncertainty
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Computation and Refinement of Statistical Bounds on Circuit Delay
Proceedings of the 40th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Toward a systematic-variation aware timing methodology
Proceedings of the 41st annual Design Automation Conference
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
On path-based learning and its applications in delay test and diagnosis
Proceedings of the 41st annual Design Automation Conference
Statistical gate delay model considering multiple input switching
Proceedings of the 41st annual Design Automation Conference
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
Placement Method Targeting Predictability Robustness and Performance
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
"AU: Timing Analysis Under Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Manufacturing-Aware Physical Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Clock Skew Analysis Considering Intra-Die Process Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Toward stochastic design for digital circuits: statistical static timing analysis
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Statistical Timing Analysis Using Bounds
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On Statistical Timing Analysis with Inter- and Intra-Die Variations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Clock skew bounds estimation under power supply and process variations
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 42nd annual Design Automation Conference
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Proceedings of the 42nd annual Design Automation Conference
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Proceedings of the 42nd annual Design Automation Conference
Advanced timing analysis based on post-OPC extraction of critical dimensions
Proceedings of the 42nd annual Design Automation Conference
Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
A path-based methodology for post-silicon timing validation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical crosstalk aggressor alignment aware interconnect delay calculation
Proceedings of the 2006 international workshop on System-level interconnect prediction
An exact algorithm for the statistical shortest path problem
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Block based statistical timing analysis with extended canonical timing model
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Hierarchical analysis of process variation for mixed-signal systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Timing analysis in presence of supply voltage and temperature variations
Proceedings of the 2006 international symposium on Physical design
Bringing Manufacturing into Design via Process-Dependent SPICE Models
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical gate delay calculation with crosstalk alignment consideration
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Statistical critical path analysis considering correlations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis with path reconvergence and spatial correlations
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 2006 ACM symposium on Applied computing
An up-stream design auto-fix flow for manufacturability enhancement
Proceedings of the 43rd annual Design Automation Conference
DFM issues for 65nm and beyond
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A framework for statistical timing analysis using non-linear delay and slew models
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A new statistical max operation for propagating skewness in statistical timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Digital Circuit Optimization via Geometric Programming
Operations Research
Proceedings of the conference on Design, automation and test in Europe
Temperature and voltage aware timing analysis: application to voltage drops
Proceedings of the conference on Design, automation and test in Europe
Fast statistical circuit analysis with finite-point based transistor model
Proceedings of the conference on Design, automation and test in Europe
A novel criticality computation method in statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modeling crosstalk in statistical static timing analysis
Proceedings of the 45th annual Design Automation Conference
Signal probability based statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Breaking the simulation barrier: SRAM evaluation through norm minimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Timing analysis with compact variation-aware standard cell models
Integration, the VLSI Journal
Finite-point-based transistor model: a new approach to fast circuit simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical timing analysis based on simulation of lithographic process
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Path criticality computation in parameterized statistical timing analysis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Fast estimation of timing yield bounds for process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Data memory subsystem resilient to process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Temperature aware statistical static timing analysis
Proceedings of the International Conference on Computer-Aided Design
Statistical critical path analysis considering correlations
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Statistical characterization of library timing performance
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Journal of Electronic Testing: Theory and Applications
International Journal of Embedded and Real-Time Communication Systems
NBTI-aware circuit node criticality computation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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The traditional approach to worst-case static-timing analysis is becoming unacceptably conservative due to an ever-increasing number of circuit and process effects. We propose a fundamentally different framework that aims to significantly improve the accuracy of timing predictions through fully probabilistic analysis of gate and path delays. We describe a bottom-up approach for the construction of joint probability density function of path delays, and present novel analytical and algorithmic methods for finding the full distribution of the maximum of a random path delay space with arbitrary path correlations.