Simultaneous driver and wire sizing for performance and power optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Efficient estimation of arc criticalities in stochastic activity networks
Management Science
Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal wiresizing for interconnects with multiple sources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interior point algorithms: theory and analysis
Interior point algorithms: theory and analysis
Exploring the design space of mixed swing QuadRail for low-power digital circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
GPCAD: a tool for CMOS op-amp synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Power-delay optimizations in gate sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Concurrent logic restructuring and placement for timing closure
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Design and optimization of LC oscillators
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
RC(L) interconnect sizing with second order considerations via posynomial programming
Proceedings of the 2001 international symposium on Physical design
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On gate level power optimization using dual-supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage control with efficient use of transistor stacks in single threshold CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 39th annual Design Automation Conference
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Design of pipeline analog-to-digital converters via geometric programming
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Standby power optimization via transistor sizing and dual threshold voltage assignment
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Realizable parasitic reduction using generalized Y-Δ transformation
Proceedings of the 40th annual Design Automation Conference
Efficient description of the design space of analog circuits
Proceedings of the 40th annual Design Automation Conference
Energy-efficient skewed static logic with dual Vt: design and synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Proceedings of the 2003 international symposium on Low power electronics and design
Automated Optimal Design of Switched-Capacitor Filters
Proceedings of the conference on Design, automation and test in Europe
Gate leakage reduction for scaled devices using transistor stacking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Delay-Optimized Implementation of IEEE Floating-Point Addition
IEEE Transactions on Computers
Timing modeling and optimization under the transmission line model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate oxide leakage current analysis and reduction for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Level conversion for dual-supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Convex Optimization
Automated design of operational transconductance amplifiers using reversed geometric programming
Proceedings of the 41st annual Design Automation Conference
ORACLE: optimization with recourse of analog circuits including layout extraction
Proceedings of the 41st annual Design Automation Conference
"AU: Timing Analysis Under Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation
Proceedings of the 2004 international symposium on Low power electronics and design
Proceedings of the 2004 international symposium on Low power electronics and design
Fitted Elmore delay: a simple and accurate interconnect delay model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High performance level conversion for dual VDD design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A New Method for Design of Robust Digital Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses
IEEE Design & Test
Analysis and Design of Digital Integrated Circuits
Analysis and Design of Digital Integrated Circuits
Noise constrained transistor sizing and power optimization for dual V/sub t/ domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire sizing as a convex optimization problem: exploring the area-delay tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal design of macrocells for low power and high speed
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The Elmore delay as a bound for RC trees with generalized input signals
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast algorithm for minimizing the Elmore delay to identified critical sinks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power buffered clock tree design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EWA: efficient wiring-sizing algorithm for signal nets and clock nets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Greedy wire-sizing is linear time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal shape function for a bidirectional wire under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient and optimal algorithm for simultaneous buffer and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalent Elmore delay for RLC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous gate sizing and placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMOS op-amp sizing using a geometric programming formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Converter-free multiple-voltage scaling techniques for low-power CMOS digital design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RC delay metrics for performance optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Handling soft modules in general nonslicing floorplan using Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical method for the analysis of interconnects delay in submicrometer layouts
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wire width planning for interconnect performance optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Slope propagation in static timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dynamic frequency scaling with buffer insertion for mixed workloads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design and optimization of multithreshold CMOS (MTCMOS) circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fanout optimization algorithm based on the effort delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimizing total power by simultaneous Vdd/Vth assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Sorter based permutation units for media-enhanced microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Device-circuit co-optimization for mixed-mode circuit design via geometric programming
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Mapping for better than worst-case delays in LUT-based FPGA designs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Robust gate sizing via mean excess delay minimization
Proceedings of the 2008 international symposium on Physical design
Low-power leading-zero counting and anticipation logic for high-speed floating point units
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion
Journal of Electronic Testing: Theory and Applications
Gate sizing for cell-library-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dominant critical gate identification for power and yield optimization in logic circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
FPGA architecture optimisation using geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Convex piecewise-linear modeling method for circuit optimization via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Finding the energy efficient curve: gate sizing for minimum power under delay constraints
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Theory and Applications of Robust Optimization
SIAM Review
A Distributional Interpretation of Robust Optimization
Mathematics of Operations Research
Methodology for energy-efficient digital circuit sizing: important issues and design limitations
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
ECO cost measurement and incremental gate sizing for late process changes
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Base-2 Expansions for Linearizing Products of Functions of Discrete Variables
Operations Research
Base-2 Expansions for Linearizing Products of Functions of Discrete Variables
Operations Research
Holistic design parameter optimization of multiple periodic resources in hierarchical scheduling
Proceedings of the Conference on Design, Automation and Test in Europe
On the maximal singularity-free ellipse of planar 3-RP R parallel mechanisms via convex optimization
Robotics and Computer-Integrated Manufacturing
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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.