Challenges in clockgating for a low power ASIC methodology
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits
IEEE Transactions on Computers
Clock-tree power optimization based on RTL clock-gating
Proceedings of the 40th annual Design Automation Conference
Power-aware clock tree planning
Proceedings of the 2004 international symposium on Physical design
Proceedings of the 42nd annual Design Automation Conference
Variation tolerant buffered clock network synthesis with cross links
Proceedings of the 2006 international symposium on Physical design
Thermal resilient bounded-skew clock tree optimization methodology
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Legitimate Skew Clock Routing with Buffer Insertion
Journal of VLSI Signal Processing Systems
Digital Circuit Optimization via Geometric Programming
Operations Research
Low-power gated and buffered clock network construction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dynamic thermal clock skew compensation using tunable delay buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Opposite-Phase Clock Tree for Peak Current Reduction
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Clock tree synthesis under aggressive buffer insertion
Proceedings of the 47th Design Automation Conference
Thermal-aware clock tree design to increase timing reliability of embedded SoCs
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Cross link insertion for improving tolerance to variations in clock network synthesis
Proceedings of the 2011 international symposium on Physical design
PASCOM: power model for supercomputers
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Fast power- and slew-aware gated clock tree synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.04 |
We address the problem of low-power reliable clock tree design in this paper. We study the scaling of clock power dissipation with increasing die sizes, number of receivers, and operating frequencies. The analysis shows that buffering only at the root of the tree is not scalable. However, when buffered clock trees are allowed, the classical H tree is suboptimal in terms of both area and power dissipation. We show that the new power minimization problem is NP hard, and we propose a novel algorithm for low-power clock network design. Our algorithm designs the tree topology and inserts buffers simultaneously. The clock skew is guaranteed to be small in the presence of correlated process variations. Wire sizing is used when necessary, and clock skew can be inserted intentionally if required. The results obtained by our algorithm on benchmark problem instances are significantly better than previous approaches in terms of power dissipation, wire length, rise times, and buffer area. We report HSPICE simulation results for the clock trees designed by the new algorithm