Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A buffer distribution algorithm for high-speed clock routing
DAC '93 Proceedings of the 30th international Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Activity-driven clock design for low power circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Challenges in clockgating for a low power ASIC methodology
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Gated clock routing minimizing the switched capacitance
Proceedings of the conference on Design, automation and test in Europe
Activity-sensitive clock tree construction for low power
Proceedings of the 2002 international symposium on Low power electronics and design
Clock-tree power optimization based on RTL clock-gating
Proceedings of the 40th annual Design Automation Conference
Buffered Clock Tree for High Quality IC Design
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Low power network processor design using clock gating
Proceedings of the 42nd annual Design Automation Conference
Low-power gated and buffered clock network construction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Type-matching clock tree for zero skew clock gating
Proceedings of the 45th annual Design Automation Conference
Ispd2009 clock network synthesis contest
Proceedings of the 2009 international symposium on Physical design
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results
Proceedings of the 19th international symposium on Physical design
Clock tree synthesis under aggressive buffer insertion
Proceedings of the 47th Design Automation Conference
Minimizing clock latency range in robust clock tree synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A dual-MST approach for clock network synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
An effective gated clock tree design based on activity and register aware placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DCG: deterministic clock-gating for low-power microprocessor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Minimal buffer insertion in clock trees with skew and slew rate constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power buffered clock tree design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gated clock routing for low-power microprocessor design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast algorithm for optimal buffer insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Clock tree synthesis plays an important role on the total performance of chip. Gated clock tree is an effective approach to reduce the dynamic power usage. In this paper, two novel gated clock tree synthesizers, power-aware clock tree synthesizer (PACTS) and power- and slew-aware clock tree synthesizer (PSACTS), are proposed with zero skew achieved based on Elmore RC model. In PACTS, the topology of the clock tree is constructed with simultaneous buffer/gate insertion, which reduces the switched capacitance. In PSACTS, a more practical clock slew constraint is applied. Compared to previous works, clock tree synthesis is done first and followed by the insertions of clock gates. The clock slew changes a lot after the insertions of clock gates in real cases. In our work, the clock tree is constructed simultaneously with the insertions of clock gates. This ensures the limitation of the clock slew can be strictly satisfied while the limitation of the clock slew is always applied in the real design. The experimental results show that the power cost of our work is smaller and the runtime is reduced. The slew rate constraint is satisfied with a small clock skew from SPICE estimation. Generally, our work has better performance, improved efficiency and is more practical to be applied in the industry.