Lower bounds for rectilinear Steiner trees in bounded space
Information Processing Letters
Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Approximating the minimum degree spanning tree to within one from the optimal degree
SODA '92 Proceedings of the third annual ACM-SIAM symposium on Discrete algorithms
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
Automatic clock tree generation in ASIC designs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Probabilistic Approach to Buffer Insertion
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A dual-MST approach for clock network synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fast power- and slew-aware gated clock tree synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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