Introduction to VLSI Systems
PROUD: A Sea-Of-Gates Placement Algorithm
IEEE Design & Test
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Reliable non-zero skew clock trees using wire width optimization
DAC '93 Proceedings of the 30th international Design Automation Conference
A buffer distribution algorithm for high-speed clock routing
DAC '93 Proceedings of the 30th international Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Low-cost single-layer clock trees with exact zero Elmore delay skew
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Skew sensitivity minimization of buffered clock tree
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Process-variation-tolerant clock skew minimization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A global router optimizing timing and area for high-speed bipolar LSI's
DAC '94 Proceedings of the 31st annual Design Automation Conference
An efficient zero-skew routing algorithm
DAC '94 Proceedings of the 31st annual Design Automation Conference
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
EURO-DAC '94 Proceedings of the conference on European design automation
Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimization of power dissipation and skew sensitivity in clock buffer synthesis
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Clock distribution design and verification for PowerPC microprocessors
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Constructing lower and upper bounded delay routing trees using linear programming
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Useful-Skew Clock Routing with Gate Sizing for Low Power Design
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A hierarchical decomposition methodology for multistage clock circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Buffer insertion for clock delay and skew minimization
ISPD '99 Proceedings of the 1999 international symposium on Physical design
A zero-skew clock routing scheme for VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Perfect-balance planar clock routing with minimal path-length
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Clock distribution using multiple voltages
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Challenges in clockgating for a low power ASIC methodology
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Minimizing wirelength in zero and bounded skew clock trees
Proceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms
A practical clock tree synthesis for semi-synchronous circuits
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Practical approximation algorithms for zero- and bounded-skew trees
SODA '01 Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms
Consistent floorplanning with super hierarchical constraints
Proceedings of the 2001 international symposium on Physical design
Optimal spacing and capacitance padding for general clock structures
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Low-power clock distribution using multiple voltages and reduced swings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Automatic clock tree generation in ASIC designs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Constructing Minimal Spanning/Steiner Trees with Bounded Path Length
EDTC '96 Proceedings of the 1996 European conference on Design and Test
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Balanced-Mesh Clock Routing Technique Using Circuit Partitioning
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On-Line Testing Scheme for Clock's Faults
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Proceedings of the 42nd annual Design Automation Conference
Multi-level genetic algorithm (MLGA) for the construction of clock binary tree
GECCO '05 Proceedings of the 7th annual conference on Genetic and evolutionary computation
Clock Distribution Architectures: A Comparative Study
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Buffered clock tree synthesis for 3D ICs under thermal variations
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm
Integration, the VLSI Journal
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Constructing minimal spanning/Steiner trees with bounded path length
Integration, the VLSI Journal
Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Fast timing-model independent buffered clock-tree synthesis
Proceedings of the 47th Design Automation Conference
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Proceedings of the Conference on Design, Automation and Test in Europe
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A dual-MST approach for clock network synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock tree embedding for 3D ICs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock network synthesis with concurrent gate insertion
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Clock Tree synthesis for TSV-based 3D IC designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
Low-power clock trees for CPUs
Proceedings of the International Conference on Computer-Aided Design
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Proceedings of the International Conference on Computer-Aided Design
A new clock network synthesizer for modern VLSI designs
Integration, the VLSI Journal
Efficient clock distribution scheme for VLSI RNS-Enabled controllers
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Top-down-based symmetrical buffered clock routing
Proceedings of the great lakes symposium on VLSI
TSV array utilization in low-power 3D clock network design
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Fast power- and slew-aware gated clock tree synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks
Integration, the VLSI Journal
| Hi-index | 0.00 |
In this paper we focus on routing techniques for optimizing clock signals in small-cell (e.g., standard-cell, sea-of gate, etc.…) ASICs. In previously reported work, the routing of the clock net has been performed using ordinary global routing techniques based on a minimum spanning or minimal Steiner tree that have little understanding of clock routing problems. We present a novel approach to clock routing that all but eliminates clock skew and yields excellent phase delay results for a wide range of chip sizes, net sizes (pin count), minimum feature sizes, and pin distributions on both randomly created and standard industrial benchmarks. For certain classes of pin distributions we have proven theoretically and observed experimentally a decrease in skew with an increase in net size. In practice, we have observed a two to three order magnitude reduction in skew when compared to a minimum rectilinear spanning tree.