Perfect-balance planar clock routing with minimal path-length

Low-cost single-layer clock trees with exact zero Elmore delay skew

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Process-variation-tolerant clock skew minimization

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

A specified delay accomplishing clock router using multiple layers

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay

EURO-DAC '94 Proceedings of the conference on European design automation

Buffer insertion and sizing under process variations for low power clock distribution

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Power optimal buffered clock tree design

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

On the bounded-skew clock and Steiner routing problems

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Bounded-skew clock and Steiner routing under Elmore delay

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Minimizing wirelength in zero and bounded skew clock trees

Proceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms