High-performance clock routing based on recursive geometric matching

Zero skew clock net routing

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

Reliable non-zero skew clock trees using wire width optimization

DAC '93 Proceedings of the 30th international Design Automation Conference

A buffer distribution algorithm for high-speed clock routing

DAC '93 Proceedings of the 30th international Design Automation Conference

A clustering-based optimization algorithm in zero-skew routings

DAC '93 Proceedings of the 30th international Design Automation Conference

Low-cost single-layer clock trees with exact zero Elmore delay skew

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Skew sensitivity minimization of buffered clock tree

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Process-variation-tolerant clock skew minimization

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

A specified delay accomplishing clock router using multiple layers

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Power optimal buffered clock tree design

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Optimization of power dissipation and skew sensitivity in clock buffer synthesis

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

A parallel algorithm for zero skew clock tree routing

ISPD '98 Proceedings of the 1998 international symposium on Physical design

Buffer insertion for clock delay and skew minimization

ISPD '99 Proceedings of the 1999 international symposium on Physical design

A zero-skew clock routing scheme for VLSI circuits

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Zero skew clock routing in multiple-clock synchronous systems

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Perfect-balance planar clock routing with minimal path-length

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Clock distribution using multiple voltages

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

Minimizing wirelength in zero and bounded skew clock trees

Proceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms

Practical approximation algorithms for zero- and bounded-skew trees

SODA '01 Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms

Low-power clock distribution using multiple voltages and reduced swings

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Automatic clock tree generation in ASIC designs

EDTC '95 Proceedings of the 1995 European conference on Design and Test

An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion

EDTC '96 Proceedings of the 1996 European conference on Design and Test

Power-aware placement

Proceedings of the 42nd annual Design Automation Conference

Multi-level genetic algorithm (MLGA) for the construction of clock binary tree

GECCO '05 Proceedings of the 7th annual conference on Genetic and evolutionary computation

Legitimate Skew Clock Routing with Buffer Insertion

Journal of VLSI Signal Processing Systems

Zero skew clock routing in X-architecture based on an improved greedy matching algorithm

Integration, the VLSI Journal

Constructing minimal spanning/Steiner trees with bounded path length

Integration, the VLSI Journal

Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design

Fast timing-model independent buffered clock-tree synthesis

Proceedings of the 47th Design Automation Conference

Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network

Proceedings of the Conference on Design, Automation and Test in Europe

Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration

Integration, the VLSI Journal

Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

A dual-MST approach for clock network synthesis

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Clock network synthesis with concurrent gate insertion

PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation

Multilevel tree fusion for robust clock networks

Proceedings of the International Conference on Computer-Aided Design

Local clock skew minimization using blockage-aware mixed tree-mesh clock network

Proceedings of the International Conference on Computer-Aided Design

A new clock network synthesizer for modern VLSI designs

Integration, the VLSI Journal

Top-down-based symmetrical buffered clock routing

Proceedings of the great lakes symposium on VLSI

Fast power- and slew-aware gated clock tree synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems