A clustering-based optimization algorithm in zero-skew routings

Low-cost single-layer clock trees with exact zero Elmore delay skew

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

An efficient zero-skew routing algorithm

DAC '94 Proceedings of the 31st annual Design Automation Conference

Power optimal buffered clock tree design

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

On the bounded-skew clock and Steiner routing problems

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Bounded-skew clock and Steiner routing under Elmore delay

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Useful-skew clock routing with gate sizing for low power design

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Jitter-tolerant clock routing in two-phase synchronous systems

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Power Optimization in VLSI Layout: A Survey

Journal of VLSI Signal Processing Systems

Useful-Skew Clock Routing with Gate Sizing for Low Power Design

Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks

Practical Bounded-Skew Clock Routing

Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks

More practical bounded-skew clock routing

DAC '97 Proceedings of the 34th annual Design Automation Conference

Clock-tree routing realizing a clock-schedule for semi-synchronous circuits

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

A hierarchical decomposition methodology for multistage clock circuits

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

A parallel algorithm for zero skew clock tree routing

ISPD '98 Proceedings of the 1998 international symposium on Physical design

Bounded-skew clock and Steiner routing

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Clock distribution using multiple voltages

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion

ISPD '00 Proceedings of the 2000 international symposium on Physical design

A practical clock tree synthesis for semi-synchronous circuits

ISPD '00 Proceedings of the 2000 international symposium on Physical design

The associative-skew clock routing problem

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Practical approximation algorithms for zero- and bounded-skew trees

SODA '01 Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms

Clustering based fast clock scheduling for light clock-tree

Proceedings of the conference on Design, automation and test in Europe

UST/DME: a clock tree router for general skew constraints

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Low-power clock distribution using multiple voltages and reduced swings

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Process variation aware clock tree routing

Proceedings of the 2003 international symposium on Physical design

Automatic clock tree generation in ASIC designs

EDTC '95 Proceedings of the 1995 European conference on Design and Test

An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion

EDTC '96 Proceedings of the 1996 European conference on Design and Test

A Balanced-Mesh Clock Routing Technique Using Circuit Partitioning

EDTC '96 Proceedings of the 1996 European conference on Design and Test

Power-aware clock tree planning

Proceedings of the 2004 international symposium on Physical design

Skew scheduling and clock routing for improved tolerance to process variations

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Process variation robust clock tree routing

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Statistical clock tree routing for robustness to process variations

Proceedings of the 2006 international symposium on Physical design

Practical techniques to reduce skew and its variations in buffered clock networks

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Integrated placement and skew optimization for rotary clocking

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Associative skew clock routing for difficult instances

Proceedings of the conference on Design, automation and test in Europe: Proceedings

An efficent clustering algorithm for low power clock tree synthesis

Proceedings of the 2007 international symposium on Physical design

Low-power gated and buffered clock network construction

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Integrated placement and skew optimization for rotary clocking

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Zero skew clock routing in X-architecture based on an improved greedy matching algorithm

Integration, the VLSI Journal

Robust chip-level clock tree synthesis for SOC designs

Proceedings of the 45th annual Design Automation Conference

Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors

Proceedings of the 2009 international symposium on Physical design

Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization

Proceedings of the 46th Annual Design Automation Conference

Fast timing-model independent buffered clock-tree synthesis

Proceedings of the 47th Design Automation Conference

Clock tree synthesis under aggressive buffer insertion

Proceedings of the 47th Design Automation Conference

Contango: integrated optimization of SoC clock networks

Proceedings of the Conference on Design, Automation and Test in Europe

Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration

Integration, the VLSI Journal

Minimizing clock latency range in robust clock tree synthesis

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

A dual-MST approach for clock network synthesis

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Clock tree embedding for 3D ICs

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Clock network synthesis with concurrent gate insertion

PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation

Cross link insertion for improving tolerance to variations in clock network synthesis

Proceedings of the 2011 international symposium on Physical design

An efficient merging scheme for prescribed skew clock routing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Clock Tree synthesis for TSV-based 3D IC designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Pulsed-latch-based clock tree migration for dynamic power reduction

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design

PRICE: power reduction by placement and clock-network co-synthesis for pulsed-latch designs

Proceedings of the International Conference on Computer-Aided Design

Multilevel tree fusion for robust clock networks

Proceedings of the International Conference on Computer-Aided Design

Low-power clock trees for CPUs

Proceedings of the International Conference on Computer-Aided Design

A new clock network synthesizer for modern VLSI designs

Integration, the VLSI Journal

On construction low power and robust clock tree via slew budgeting

Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design

Top-down-based symmetrical buffered clock routing

Proceedings of the great lakes symposium on VLSI

Synchronization scheme for brick-based rotary oscillator arrays

Proceedings of the great lakes symposium on VLSI

Clock tree synthesis with methodology of re-use in 3D IC

Proceedings of the 49th Annual Design Automation Conference

Sparse-rotary oscillator array (SROA) design for power and skew reduction

Proceedings of the Conference on Design, Automation and Test in Europe

Fast power- and slew-aware gated clock tree synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization

ACM Transactions on Design Automation of Electronic Systems (TODAES)